KR960043066A - Test method using test pattern for diffusion evaluation - Google Patents

Test method using test pattern for diffusion evaluation Download PDF

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Publication number
KR960043066A
KR960043066A KR1019950012901A KR19950012901A KR960043066A KR 960043066 A KR960043066 A KR 960043066A KR 1019950012901 A KR1019950012901 A KR 1019950012901A KR 19950012901 A KR19950012901 A KR 19950012901A KR 960043066 A KR960043066 A KR 960043066A
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KR
South Korea
Prior art keywords
junction region
substrate
pattern
test
gate pattern
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Application number
KR1019950012901A
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Korean (ko)
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KR0179172B1 (en
Inventor
송주현
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문정환
Lg 반도체주식회사
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Priority to KR1019950012901A priority Critical patent/KR0179172B1/en
Publication of KR960043066A publication Critical patent/KR960043066A/en
Application granted granted Critical
Publication of KR0179172B1 publication Critical patent/KR0179172B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 발명은 확산 평가용 테스트패턴을 이용한 테스트방법에 관한 것으로, 기판에 매립된 도전층을 이용하여 측면확산 및 접합깊이를 용이하게 측정해내기 위한 것이다.The present invention relates to a test method using a test pattern for diffusion evaluation, and to easily measure side diffusion and junction depth using a conductive layer embedded in a substrate.

본 발명은 기판상에 형성된 소정의 게이트패턴과, 상기 게이트패턴 양단의 기판 부위에 각각 형성된 불순물 접합영역, 및 상기 불순물 접합영역 사이의 상기 게이트패턴 하부의 기판영역내에 수직으로 매립되어 형성된 도전층으로 이루어진 테스트 패턴을 형성하고, 상기 테스트패턴의 도전층과 불순물 접합영역간의 전기적인 도통검사를 실시하는 것을 특징으로 하는 확산평가용 테스트 패턴을 이용한 테스트방법을 제공한다.The present invention relates to a conductive layer formed by filling a predetermined gate pattern formed on a substrate, an impurity junction region formed on a substrate portion across the gate pattern, and a substrate region below the gate pattern between the impurity junction region. It provides a test method using a test pattern for diffusion evaluation characterized in that the formed test pattern, and conducting electrical conduction test between the conductive layer and the impurity junction region of the test pattern.

Description

확산평가용 테스트패턴을 이용한 테스트방법Test method using test pattern for diffusion evaluation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 확산평가용 테스트패턴의 단면구조도.3 is a cross-sectional structure diagram of the test pattern for diffusion evaluation according to the present invention.

Claims (3)

기판상에 형성된 소정의 게이트패턴과, 상기 게이트패턴 양단의 기판 부위에 각각 형성된 불순물 접합영역, 및 상기 불순물 접합영역 사이의 상기 게이트패턴 하부의 기판영역내에 수직으로 매립되어 형성된 도전층으로 이루어진 테스트 패턴을 형성하고, 상기 테스트패턴의 도전층과 불순물 접합영역간의 전기적인 도통검사를 실시하는 것을 특징으로 하는 확산평가용 테스트패턴을 이용한 테스트방법.A test pattern comprising a predetermined gate pattern formed on a substrate, an impurity junction region formed on each of the substrate portions at both ends of the gate pattern, and a conductive layer vertically buried in the substrate region below the gate pattern between the impurity junction region; And conducting an electrical conduction test between the conductive layer of the test pattern and the impurity junction region of the test pattern. 기판상에 형성된 소정의 게이트패턴과, 상기 게이트패턴 양단의 기판 부위에 각각 형성된 불순물 접합영역, 및 상기불순물 접합영역 사이의 상기 게이트패턴 하부의 기판영역내에 매립되어 형성된 도전층으로 이루어진 테스트 패턴을 형성하고, 상기 도전층의 끝단에서 상기 게이트패턴의 끝단까지의 거리와, 상기 불순물 접합영역의 확산거리로부터 상기 불순물 접합영역 사이의 길이를 구하는 것을 특징으로 하는 확산평가용 테스트패턴을 이용한 테스트방법.Forming a test pattern comprising a predetermined gate pattern formed on a substrate, an impurity junction region formed on each of the substrate portions across the gate pattern, and a conductive layer formed in the substrate region below the gate pattern between the impurity junction region; And a distance from the end of the conductive layer to the end of the gate pattern and the length of the impurity junction region from the diffusion distance of the impurity junction region is obtained. 기판상에 형성된 소정의 게이트패턴과, 상기 게이트패턴 양단의 기판 부위에 각각 형성된 불순물을 접합영역, 및 상기 불순물 접합영역 하부의 기판영역에 매립되어 형성된 도전층으로 이루어진 확산평가용 테스트패턴을 형성하고, 상기 도전층의 상부에 상기 게이트패턴 하부까지의 거리와, 상기 불순물 접합영역의 확산거리로부터 상기 불순물 접합영역의 깊이를 구하는 것을 특징으로 하는 확산평가용 태스트패턴을 이용한 테스트방법.Forming a diffusion pattern test pattern comprising a predetermined gate pattern formed on a substrate, a junction region formed on each of the substrate portions at both ends of the gate pattern, and a conductive layer formed by filling a substrate region below the impurity junction region; And a depth of the impurity junction region is obtained from a distance from an upper portion of the conductive layer to a lower portion of the gate pattern and a diffusion distance of the impurity junction region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950012901A 1995-05-23 1995-05-23 Test method using test pattern KR0179172B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950012901A KR0179172B1 (en) 1995-05-23 1995-05-23 Test method using test pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950012901A KR0179172B1 (en) 1995-05-23 1995-05-23 Test method using test pattern

Publications (2)

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KR960043066A true KR960043066A (en) 1996-12-23
KR0179172B1 KR0179172B1 (en) 1999-04-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324324B1 (en) * 1999-08-26 2002-02-16 김영환 Test pattern for hot carrier in mos transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324324B1 (en) * 1999-08-26 2002-02-16 김영환 Test pattern for hot carrier in mos transistor

Also Published As

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KR0179172B1 (en) 1999-04-15

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