KR960026192A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR960026192A
KR960026192A KR1019940037679A KR19940037679A KR960026192A KR 960026192 A KR960026192 A KR 960026192A KR 1019940037679 A KR1019940037679 A KR 1019940037679A KR 19940037679 A KR19940037679 A KR 19940037679A KR 960026192 A KR960026192 A KR 960026192A
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KR
South Korea
Prior art keywords
forming
metal film
film
metal
metal wiring
Prior art date
Application number
KR1019940037679A
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Korean (ko)
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940037679A priority Critical patent/KR960026192A/en
Publication of KR960026192A publication Critical patent/KR960026192A/en

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Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 있어서; 제1절연막으로 절연된 전도층의 예정된 금속콘택 부위에 접촉창을 형성하는 단계; 전체구조 상부 표면을 따라 상기 접촉성이 매립되지 않을 정도의 일정두께로 제1금속막을 형성하는 단계; 상기 제1금속막에 의해 채워지지 않은 접촉창 내부에 제2절연막을 매립하는 단계; 전체구조 상부에 주금속배선막인 제2금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법에 관한 것으로, 초미세콘택홀에 의한 다층금속배선을 플러그 물질의 잔류물 없이 형성함으로써, 반도체 소자의 신뢰성을 향상시키는 효과를 가져온다.The present invention provides a method for forming metal wiring of a semiconductor device; Forming a contact window on a predetermined metal contact portion of the conductive layer insulated with the first insulating film; Forming a first metal film with a predetermined thickness such that the contact is not buried along the upper surface of the entire structure; Embedding a second insulating film in a contact window not filled by the first metal film; A method of forming a metal wiring of a semiconductor device, the method comprising forming a second metal film as a main metal wiring film on an entire structure, wherein the multilayer metal wiring by an ultra-fine contact hole is formed without residue of a plug material. Formation brings about the effect of improving the reliability of a semiconductor element.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 일실시예에 따른 금속배선 형성 공정도.2A to 2D are metal wiring forming process diagrams according to one embodiment of the present invention.

Claims (7)

반도체 소자의 금속배선 형성방법에 있어서; 제1절연막으로 절연된 전도층의 예정된 금속콘택 부위에 접촉창을 형성하는 단계; 전체구조 상부 표면을 따라 상기 접촉창이 매립되지 않을 정도의 일정두께로 제1금속막을 형성하는 단계; 상기 제1금속막에 의해 채워지지 않은 접촉창 내부에 제2절연막을 매립하는 단계; 전체구조 상부에 주금속배선막인 제2금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.A metal wiring forming method of a semiconductor device; Forming a contact window on a predetermined metal contact portion of the conductive layer insulated with the first insulating film; Forming a first metal film at a predetermined thickness such that the contact window is not buried along the upper surface of the entire structure; Embedding a second insulating film in a contact window not filled by the first metal film; Forming a second metal film as a main metal wiring film on the entire structure. 제1항에 있어서; 상기 제1금속막은 텅스텐막인 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of claim 1; And the first metal film is a tungsten film. 제1항에 있어서; 상기 제1금속막 하부에 장벽금속용 제3금속막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of claim 1; And forming a third metal film for the barrier metal under the first metal film. 제1항에 있어서; 상기 제2금속막 상부에 비반사층용 제4금속막을 더 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of claim 1; And forming a fourth metal film for an anti-reflective layer on the second metal film. 제3항에 있어서; 상기 제2금속막 상부에 비반사층용 제4금속막을 더 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성 방법.The method of claim 3; And forming a fourth metal film for an anti-reflective layer on the second metal film. 제3항 내지 제5항 중 어느 한 항에 있어서; 상기 제2금속막 형성 이전에 상기 제1금속막과의 접착력을 향상시키기 위한 제5금속막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method according to any one of claims 3 to 5; And forming a fifth metal film to improve adhesion to the first metal film before forming the second metal film. 제6항에 있어서; 상기 제5금속막은 TiW막인 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of claim 6; And the fifth metal film is a TiW film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037679A 1994-12-28 1994-12-28 Metal wiring formation method of semiconductor device KR960026192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940037679A KR960026192A (en) 1994-12-28 1994-12-28 Metal wiring formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940037679A KR960026192A (en) 1994-12-28 1994-12-28 Metal wiring formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR960026192A true KR960026192A (en) 1996-07-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940037679A KR960026192A (en) 1994-12-28 1994-12-28 Metal wiring formation method of semiconductor device

Country Status (1)

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KR (1) KR960026192A (en)

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