KR930003279A - Surface planarization method of semiconductor device - Google Patents

Abstract

No content.

Description

Surface planarization method of semiconductor device

Since this is an open matter, no full text was included.

3A to 3E are cross-sectional views for explaining the surface leveling method of a semiconductor device according to the present invention.

Claims (8)

In the planarization process of the insulating layer between conductive layers of a semiconductor device having a multi-layered wiring structure, a step of depositing a first insulating layer for preventing corrosion of a thin film on a conductive layer, and a space between the conductive layers on which the first insulating layer is deposited. Filling the buried material having high fluidity to a predetermined height, forming a second insulating layer on the buried material layer and the first insulating layer, forming a third insulating layer having high fluidity on the second insulating layer, And forming a fourth insulating layer on the third insulating layer. 2. The method of claim 1, wherein the conductive layer is an Al or Al alloy layer. The method of claim 1, wherein the first insulating layer is a CVD oxide film. The method of claim 1, wherein the buried material is SOG or boton oxide (B ₂ O ₃ ) having a very high fluidity. The method of claim 1, wherein the second insulating layer is a plasma-TEOS oxide film. The method of claim 1, wherein the third insulating layer is SOG having high fluidity. The method of claim 1, wherein the fourth insulating layer is a plasma-SiH ₄ oxide film. 2. The method of claim 1, wherein the space size between the conductive layers is less than half micron. ※ Note: The disclosure is based on the initial application.