KR940001280A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940001280A
KR940001280A KR1019920010945A KR920010945A KR940001280A KR 940001280 A KR940001280 A KR 940001280A KR 1019920010945 A KR1019920010945 A KR 1019920010945A KR 920010945 A KR920010945 A KR 920010945A KR 940001280 A KR940001280 A KR 940001280A
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KR
South Korea
Prior art keywords
forming
recess
contact hole
manufacturing
semiconductor device
Prior art date
Application number
KR1019920010945A
Other languages
Korean (ko)
Other versions
KR100265749B1 (en
Inventor
박동건
이태우
김선준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920010945A priority Critical patent/KR100265749B1/en
Publication of KR940001280A publication Critical patent/KR940001280A/en
Application granted granted Critical
Publication of KR100265749B1 publication Critical patent/KR100265749B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 기판상에 절연층을 형성하고, 상기 절연막에 요부를 형성하고, 상기 요부에 콘택홀을 형성하고, 상기 콘택홀을 도전성 물질로 매립함을 특징으로 하는 반도체 장치의 제조방법을 제공한다.The present invention provides a method for manufacturing a semiconductor device, comprising forming an insulating layer on a semiconductor substrate, forming a recess in the insulating film, forming a contact hole in the recess, and filling the contact hole with a conductive material. do.

본 발명에 따라서 배선형성공정을 실시하는 경우 다층배선공정에서의 하부구조물의 요철정도가 완화되어, 패시베이션 막이나 층간절연막의 형성이 용이하게 되어 후속공정을 용이하게 진행할 수 있다.In the case of performing the wiring forming process according to the present invention, the degree of irregularities of the lower structure in the multilayer wiring process is alleviated, so that the passivation film or the interlayer insulating film can be easily formed, and the subsequent process can be easily performed.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도 내지 제11도는 본 발명의 배선형성방법을 설명하기 위한 개략도이다.6 to 11 are schematic diagrams for explaining the wiring forming method of the present invention.

Claims (6)

반도체 기판상에 절연층을 형성하고, 상기 절연막에 요부를 형성하고, 상기 요부에 콘택홀을 형성하고 상기 콘택홀을 도전성 물질로 매립함을 특징으로 하는 반도체 장치의 제조방법.Forming an insulating layer on the semiconductor substrate, forming a recess in the insulating film, forming a contact hole in the recess, and filling the contact hole with a conductive material. 제1항에 있어서, 상기 절연충이 서로다른 2종류이상의 절연층으로 구성된 복합층 임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said insulating worm is a composite layer composed of two or more kinds of different insulating layers. 제1항 또는 제2항에 있어서, 상기 절연층이 BPSG, PSG, CVD-SiO2또는 질화실리콘으로 구성된 것임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the insulating layer is composed of BPSG, PSG, CVD-SiO 2 or silicon nitride. 제1항에 있어서, 상기 콘택홀을 서로다른 2종류 이상의 도전성 물질을 사용하여 매립함을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, wherein the contact hole is buried using two or more different conductive materials. 제1항 또는 제4항에 있어서, 상기 도전성 물질이 폴리실리콘, 알루미늄, 알루미늄 합금 또는 금속 실리사이드 임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1 or 4, wherein the conductive material is polysilicon, aluminum, aluminum alloy or metal silicide. 반도체 기판상에 절연층을 형성하고, 상기 절연막에 요부를 형성하고, 상기 요부의 일부 부위에는 콘택홀을 형성하고, 상기 콘택홀 및 요부를 도전성 물질로 매립한 후 패터닝하여 금속배선공정을 수행함을 특징으로 하는 반도체 장치의 제조방법.Forming an insulating layer on the semiconductor substrate, forming a recess in the insulating layer, forming a contact hole in a portion of the recess, filling the contact hole and the recess with a conductive material, and then patterning the metal layer to perform metal wiring. A method for manufacturing a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920010945A 1992-06-23 1992-06-23 Method of fabricating metal line of semiconductor device KR100265749B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920010945A KR100265749B1 (en) 1992-06-23 1992-06-23 Method of fabricating metal line of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920010945A KR100265749B1 (en) 1992-06-23 1992-06-23 Method of fabricating metal line of semiconductor device

Publications (2)

Publication Number Publication Date
KR940001280A true KR940001280A (en) 1994-01-11
KR100265749B1 KR100265749B1 (en) 2000-10-02

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Application Number Title Priority Date Filing Date
KR1019920010945A KR100265749B1 (en) 1992-06-23 1992-06-23 Method of fabricating metal line of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100339433B1 (en) * 1999-12-30 2002-05-31 박종섭 Metal line of semiconductor device and method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787155A (en) * 1980-11-20 1982-05-31 Seiko Epson Corp Manufacture of semiconductor device
JPS63102340A (en) * 1986-10-20 1988-05-07 Matsushita Electronics Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100339433B1 (en) * 1999-12-30 2002-05-31 박종섭 Metal line of semiconductor device and method for fabricating the same

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Publication number Publication date
KR100265749B1 (en) 2000-10-02

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