KR960042441A - ID interface device - Google Patents

ID interface device Download PDF

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Publication number
KR960042441A
KR960042441A KR1019950011842A KR19950011842A KR960042441A KR 960042441 A KR960042441 A KR 960042441A KR 1019950011842 A KR1019950011842 A KR 1019950011842A KR 19950011842 A KR19950011842 A KR 19950011842A KR 960042441 A KR960042441 A KR 960042441A
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KR
South Korea
Prior art keywords
pci
isa
address
data
storage means
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Application number
KR1019950011842A
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Korean (ko)
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KR0173560B1 (en
Inventor
신동우
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950011842A priority Critical patent/KR0173560B1/en
Publication of KR960042441A publication Critical patent/KR960042441A/en
Application granted granted Critical
Publication of KR0173560B1 publication Critical patent/KR0173560B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

본 발명은 컴퓨터 주변장치를 로컬 버스상에서 제어하기 위한 IDE(Intehrated Drive Electronics) 인터페이스 장치에 관한 것으로, 외부의 PCI(Peripheral Component Interconnector) 로컬 버스로부터 PCI 데이터를 입력받아 저장하는 데이터저장수단(1); 상기 PCI 로컬 버스에 연결되어 PCI 제어신호에 따라 입력되는 PCI 주소신호를 저장하는 주소 저장수단(2);상기 PCI 로컬 버스로부터 입력되는 PCI 제어신호를 래치하는 래치수단; 상기 데이터 저장수단, 주소 저장수단, 래치수단및 외부의 ISA(Industry-Standard Architecture) 버스로부터 입력되는 신호들을 외부의 클럭신호(CLK)에 따라 정합 처리하는 ISA 브리지(9); 상기 ISA 브리지(9)에 연결되어 데이터 및 주소신호를 PCI 로컬 버스로 출력하는 멀티플렉서;를 구비하는 것을 특징으로 하여 보드 제작시 소모되는 시간 및 원가를 상당분 절감할 수 있는 효과가 있다.The present invention relates to an IDE (Intehrated Drive Electronics) interface device for controlling a computer peripheral device on a local bus, comprising: data storage means (1) for receiving and storing PCI data from an external Peripheral Component Interconnector (PCI) local bus; Address storage means (2) connected to the PCI local bus and storing a PCI address signal input according to a PCI control signal; latch means for latching a PCI control signal input from the PCI local bus; An ISA bridge (9) for matching and processing signals input from the data storage means, address storage means, latch means, and an external Industry-Standard Architecture (ISA) bus according to an external clock signal (CLK); And a multiplexer connected to the ISA bridge 9 to output data and address signals to the PCI local bus. Thus, the time and cost consumed when manufacturing the board can be substantially reduced.

Description

아이디이(IDE) 인터페이스 장치ID interface device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 구성 블럭도.1 is a block diagram of the configuration according to the present invention.

Claims (3)

외부의 PCI(Peripheral Component Interconnector) 로컬 버스로 부터 PCI 데이터를 입력받아 저장하는 데이터 저장수단; 상기 PCI 로컬 버스에 연결되어 PCI제어신호에 따라 입력되는 PCI 주소신호를 저장하는 주소 저장수단;상기 PCI 로컬 버스로 부터 입력되는 PCI 제어신호를 래치하는 래치수단; 상기 데이터 저장수단, 주소 저장수단, 래치수단 및 외부의 ISA(Industry-Standard Architecture) 버스로 부터 입력되는 신호들을 외부의 클럭신호(CLK)에 따라 정합처리하는 ISA 브리지; 상기 ISA 브리지에 연결되어 데이터 및 주소신호를 PCI 로컬 버스로 출력하는 멀티플렉서를 구비하는 것을 특징으로 하는 IDE(Integrated Drive Electronics) 인터페이스 장치.Data storage means for receiving and storing PCI data from an external Peripheral Component Interconnect (PCI) local bus; Address storage means connected to the PCI local bus and storing a PCI address signal input according to a PCI control signal; latch means for latching a PCI control signal input from the PCI local bus; An ISA bridge for matching signals input from the data storage means, the address storage means, the latch means, and an external industry-standard architecture (ISA) bus according to an external clock signal (CLK); An integrated drive electronics (IDE) interface device coupled to the ISA bridge for outputting data and address signals to a PCI local bus. 제1항에 있어서, 상기 래치수단은, 상기 PCI 제어신호중 바이트 인에이블 신호(Byte Inable Signal)를 래치하는 상태래치부(status latch); 상기 PCI 제어신호중 명령신호를 래치하는 명령래치부;를 구비하는 것을 특징으로 하는 IDE 인터페이스 장치.The apparatus of claim 1, wherein the latch unit comprises: a status latch unit configured to latch a byte enable signal among the PCI control signals; And an instruction latch unit configured to latch a command signal among the PCI control signals. 제2항에 있어서, 상기 ISA 브리지는, 상기 데이터 저장수단으로 부터 데이터를 입력받아 상기 ISA 버스로출력하고 ISA 버스로부터 입력되는 ISA 데이터와 주소신호를 상기 멀티플렉서로 출력하는 데이터 및 주소 버퍼; 상기 명령래치부의 명령신호에 따라 주소 저장수단으로부터 출력되는 주소 신호를 ISA 버스로 출력하는 ISA 주소 복호기; 상기클럭신호(CLK)에 따라 상기 바이트 인에이블 신호(Byte Inable Signal)와 명령신호를 입력받아 상기 바이트 인에이블 신호로 상기 멀티플렉서와 데이터 및 주소 버퍼를 제어하고 상기 명령신호를 ISA 버스로 출력하는 ISA 타이밍 제어 및 명령복호기;를 구비하는 것을 특징으로 하는 IDE 인터페이스 장치.3. The apparatus of claim 2, wherein the ISA bridge comprises: a data and address buffer for receiving data from the data storage means and outputting the data to the ISA bus and outputting ISA data and address signals input from the ISA bus to the multiplexer; An ISA address decoder for outputting an address signal output from an address storing means to an ISA bus according to the command signal of the command latch unit; ISA for receiving the byte enable signal and the command signal according to the clock signal CLK to control the multiplexer, the data and the address buffer with the byte enable signal, and output the command signal to the ISA bus. And an timing decoder and a command decoder. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950011842A 1995-05-13 1995-05-13 ID interface device KR0173560B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950011842A KR0173560B1 (en) 1995-05-13 1995-05-13 ID interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950011842A KR0173560B1 (en) 1995-05-13 1995-05-13 ID interface device

Publications (2)

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KR960042441A true KR960042441A (en) 1996-12-21
KR0173560B1 KR0173560B1 (en) 1999-04-01

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