KR20010036453A - Circuit for selecting counter input - Google Patents

Circuit for selecting counter input Download PDF

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Publication number
KR20010036453A
KR20010036453A KR1019990043478A KR19990043478A KR20010036453A KR 20010036453 A KR20010036453 A KR 20010036453A KR 1019990043478 A KR1019990043478 A KR 1019990043478A KR 19990043478 A KR19990043478 A KR 19990043478A KR 20010036453 A KR20010036453 A KR 20010036453A
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South Korea
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inverter
output
control signal
read
counter
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KR1019990043478A
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Korean (ko)
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연제안
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김영환
현대반도체 주식회사
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Priority to KR1019990043478A priority Critical patent/KR20010036453A/en
Publication of KR20010036453A publication Critical patent/KR20010036453A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A circuit for selecting input of a counter is provided to make input of the counter open only upon provision of read command and write command. CONSTITUTION: The first inverter(10) inverts a write control signal attached to write command to output it. The second inverter(20) a read control signal attached to read command to output it. The first clocked inverter(30) is on/off-controlled by the output from the first inverter and inverts a write address to output it. The second clocked inverter(40) is on/off-controlled by the output from the second inverter and inverts a read address to output it. The third inverter(50) inverts the output from the each clocked inverters to output it as a counter input signal.

Description

카운터입력 선택회로{CIRCUIT FOR SELECTING COUNTER INPUT}Counter input selection circuit {CIRCUIT FOR SELECTING COUNTER INPUT}

본 발명은 디램(DRAM)의 카운터회로에 관한 것으로, 특히 디램에서 외부 어드레스를 입력받아 이를 카운터의 입력으로 사용할 때, 읽기 명령 혹은 쓰기 명령이 있을 때에만 카운터의 입력이 각기 개방되도록 하는 카운터입력 선택회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit of a DRAM. In particular, when an external address is received from the DRAM and used as a counter input, a counter input selection is made so that the input of the counter is opened only when there is a read command or a write command. It is about a circuit.

일반적으로, 외부 어드레스 핀(Pin)으로 입력된 어드레스 데이터는 읽기시에 이용되는 어드레스 데이터인 읽기 어드레스(TLA계 어드레스)와 쓰기시에 이용되는 어드레스 데이터인 쓰기 어드레스(LA계 어드레스)로 나누어지는데, 디램에서는 입력된 명령어에 따라 상기 어드레스 데이터(TLA,LA)를 입력받아 카운터(도면 미도시)를 구동한다.In general, address data input to an external address pin is divided into a read address (TLA system address) which is address data used for reading and a write address (LA system address) which is address data used for writing. In the DRAM, a counter (not shown) is driven by receiving the address data TLA and LA according to the input command.

도1은 종래 카운터입력 선택회로의 회로도로서, 이에 도시된 바와 같이 읽기 명령에 첨부된 읽기제어신호(RDY)를 반전하여 출력하는 제1인버터(1)와; 읽기제어신호(RDY)와 상기 제1인버터(1)에서 반전된 읽기제어신호(RDY)에 의해 온/오프 제어되어, 쓰기 어드레스(LA)를 반전하여 출력하는 제1클럭드(CLOCKED) 인버터(2)와; 읽기제어신호(RDY)에 의해 상기 제1클럭드 인버터(2)와 교번 동작하도록 온/오프 제어되어, 읽기 어드레스(TLA)를 반전하여 출력하는 제2클럭드 인버터(3)와; 상기 각 클럭드 인버터(2,3)의 출력을 입력받아 이를 반전하여 카운터입력신호(YiT)로 출력하는 제2인버터(4)로 구성된 것으로, 이와 같이 구성된 종래 장치의 동작을 상세히 설명하면 다음과 같다.FIG. 1 is a circuit diagram of a conventional counter input selection circuit, and as shown therein, a first inverter 1 for inverting and outputting a read control signal RDY attached to a read command; A first clock (CLOCKED) inverter that is turned on / off by a read control signal RDY and a read control signal RDY inverted by the first inverter 1, and inverts and outputs a write address LA. 2) and; A second clock inverter (3) which is on / off controlled to alternately operate with the first clock inverter (2) by a read control signal (RDY), and inverts and outputs a read address (TLA); It is composed of a second inverter (4) for receiving the output of the clocked inverter (2, 3) and inverts it and outputs it as a counter input signal (YiT). same.

읽기 명령에 첨부된 읽기제어신호(RDY)가 ″하이″가 되면, 제2클럭드 인버터(3)는 읽기제어신호(RDY)와 이를 제1인버터(1)에서 반전한 출력을 각기 부단자와 정단자에 입력받아 턴온되어 읽기 어드레스(TLA)를 반전하여 제2인버터(4)로 출력하고, 이에 따라 제2인버터(4)에서 다시 반전된 읽기 어드레스(TLA)가 카운터입력신호(Yit)로 카운터(도면 미도시)에 입력된다.When the read control signal RDY attached to the read command becomes ″ high ″, the second clock inverter 3 converts the read control signal RDY and the output inverted from the first inverter 1 into a negative terminal. The input address is turned on to be inverted and the read address TLA is inverted and output to the second inverter 4. Accordingly, the read address TLA inverted again by the second inverter 4 is converted into the counter input signal Yit. It is input to a counter (not shown).

여기서, 제1클럭드 인버터(2)는 ″하이″인 읽기제어신호(RDY)에 의해 턴오프 상태에 있게 된다.Here, the first clock inverter 2 is turned off by the read control signal RDY which is " high ".

한편, 읽기 명령이 없을 때에는 읽기제어신호(RDY)가 ″로우″가 되어 제1클럭드 인버터(2)는 턴온 상태에 있고 제2클럭드 인버터(3)는 턴오프 상태에 있게 되는데, 여기서 상기 제1클럭드 인버터(2)에서 반전된 쓰기 어드레스(LA)가 제2인버터(4)를 통해 카운터입력신호(Yit)로 하여 카운터(도면 미도시)에 입력된다.On the other hand, when there is no read command, the read control signal RDY becomes ″ low ″ so that the first clock inverter 2 is turned on and the second clock inverter 3 is turned off. The write address LA inverted by the first clock inverter 2 is input to the counter (not shown) as the counter input signal Yit through the second inverter 4.

그러나, 상기에서와 같이 종래의 기술에 있어서, 카운터가 읽기 명령에 첨부된 읽기제어신호에 의해 제어되어 읽기 혹은 쓰기 어드레스를 입력받아 구동됨으로써, 읽기제어신호에 오류가 발생할 경우 카운터가 오동작하는 것은 물론, 읽기 명령과 쓰기 명령이 없는 경우에도 카운터가 동작대기중에 있게 되어 전력소모를 유발하는 문제점이 있었다.However, in the conventional technology as described above, the counter is controlled by a read control signal attached to a read command and driven by receiving a read or write address, so that the counter malfunctions when an error occurs in the read control signal. In the absence of a read command and a write command, the counter is in standby mode, causing power consumption.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창출한 것으로, 읽기 명령 혹은 쓰기 명령이 있을 때에만 카운터의 입력이 각기 개방되도록 하는 카운터입력 선택회로를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a counter input selection circuit for opening a counter input only when there is a read command or a write command.

도1은 종래 카운터입력 선택회로의 회로도.1 is a circuit diagram of a conventional counter input selection circuit.

도2는 본 발명 카운터입력 선택회로의 회로도.2 is a circuit diagram of a counter input selection circuit of the present invention.

도3은 도2에서, 읽기제어신호 및 쓰기제어신호에 따른 카운터입력신호의 동작흐름을 나타낸 타이밍도.3 is a timing diagram showing an operation flow of a counter input signal according to a read control signal and a write control signal in FIG.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

10 : 제1인버터 20 : 제2인버터10: first inverter 20: second inverter

30 : 제1클럭드 인버터 40 : 제2클럭드 인버터30: first clock inverter 40: second clock inverter

50 : 제3인버터50: third inverter

이와 같은 목적을 달성하기 위한 본 발명은, 쓰기 명령에 첨부된 쓰기제어신호를 반전하여 출력하는 제1인버터와; 읽기 명령에 첨부된 읽기제어신호를 반전하여 출력하는 제2인버터와; 쓰기제어신호와 상기 제1인버터의 출력에 의해 온/오프 제어되어 쓰기 어드레스를 반전하여 출력하는 제1클럭드 인버터와; 읽기제어신호와 상기 제2인버터의 출력에 의해 온/오프 제어되어, 읽기 어드레스를 반전하여 출력하는 제2클럭드 인버터와; 상기 각 클럭드 인버터의 출력을 반전하여 카운터입력신호로 출력하는 제3인버터로 구성한 것을 특징으로 한다.The present invention for achieving the above object, the first inverter for inverting and outputting the write control signal attached to the write command; A second inverter for inverting and outputting the read control signal attached to the read command; A first clock inverter controlled on / off by a write control signal and an output of the first inverter to invert and output a write address; A second clock inverter controlled on / off by a read control signal and an output of the second inverter, and outputting the read address by inverting the read address; And a third inverter for inverting the output of each clocked inverter and outputting the counter input signal.

이하, 본 발명에 따른 일실시예를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

도2는 본 발명 카운터입력 선택회로의 회로도로서, 이에 도시한 바와 같이 쓰기 명령에 첨부된 쓰기제어신호(WTY)를 반전하여 출력하는 제1인버터(10)와; 쓰기제어신호(WTY)와 상기 제1인버터(10)에서 반전된 쓰기제어신호(WTY)에 의해 온/오프 제어되어, 쓰기 어드레스(LA)를 반전하여 출력하는 제1클럭드(CLOCKED) 인버터(30)와; 읽기 명령에 첨부된 읽기제어신호(RDY)를 반전하여 출력하는 제2인버터(20)와; 읽기제어신호(RDY)와 상기 제2인버터(20)에서 반전된 읽기제어신호(RDY)에 의해 온/오프 제어되어, 읽기 어드레스(TLA)를 반전하여 출력하는 제2클럭드 인버터(40)와; 상기 클럭드 인버터(30,40)의 출력을 반전하여 카운터입력신호(YiT)로 출력하는 제3인버터(50)로 구성하며, 이와 같이 구성한 본 발명에 따른 일실시예의 동작 및 작용을 상세히 설명하면 다음과 같다.Fig. 2 is a circuit diagram of the counter input selection circuit of the present invention, as shown therein; a first inverter 10 for inverting and outputting a write control signal WTY attached to a write command; A first clock (CLOCKED) inverter on / off controlled by the write control signal WTY and the write control signal WTY inverted by the first inverter 10 to invert and output the write address LA. 30); A second inverter 20 which inverts and outputs the read control signal RDY attached to the read command; A second clock inverter 40 on / off controlled by the read control signal RDY and the read control signal RDY inverted by the second inverter 20 to invert and output the read address TLA; ; Inverting the output of the clocked inverter (30, 40) is configured as a third inverter (50) for outputting as a counter input signal (YiT), described in detail the operation and operation of the embodiment according to the present invention As follows.

읽기 동작을 할 경우 읽기 명령에 첨부된 읽기제어신호(RDY)가 ″하이″가 되고, 쓰기제어신호(WTY)는 ″로우″가 되는데, 이에 따라 제2클럭드 인버터(40)는 정단자에 ″하이″가 입력되고 부단자에 제2인버터(20)에서 반전한 ″로우″인 읽기제어신호(RDY)가 입력되어 턴온 되고, 제1클럭드 인버터(30)는 정단자에 ″로우″가 입력되고 부단자에 ″하이″가 입력되어 턴오프 된다.When the read operation is performed, the read control signal RDY attached to the read command becomes ″ high ″ and the write control signal WTY becomes ″ low ″. Accordingly, the second clock inverter 40 is connected to the positive terminal. ″ High ″ is inputted and the read control signal RDY which is ″ low ″ inverted by the second inverter 20 is input to the negative terminal. The first clock inverter 30 is turned ″ low ″ to the positive terminal. Input and ″ high ″ is entered at the sub-terminal to be turned off.

그리고, 읽기 어드레스(TLA)가 턴온 상태에 있는 상기 제2클럭드 인버터(40)에서 반전되어 제3인버터(50)로 출력되고, 상기 제3인버터(50)는 이를 다시 반전하여 도3의 (C)부분과 같이 카운터(도면 미도시)로 카운터입력신호(YiT)를 출력한다.In addition, the read address TLA is inverted from the second clock inverter 40 in the turned-on state and output to the third inverter 50, and the third inverter 50 inverts it again, so that The counter input signal YiT is outputted to the counter (not shown) as in the C) part.

한편, 쓰기 동작을 할 경우 쓰기 명령에 첨부된 쓰기제어신호(WTY)가 ″하이″가 되고, 읽기제어신호(RDY)는 ″로우″가 되는데, 이에 따라 제1클럭드 인버터(30)는 정단자에 ″하이″가 입력되고 부단자에 쓰기제어신호(WTY)를 제1인버터(10)에서 반전한 ″로우″가 입력되어 턴온 되고, 제2클럭드 인버터(40)는 정단자에 ″로우″가 입력되고 부단자에 ″하이″가 입력되어 턴오프 된다.On the other hand, when the write operation is performed, the write control signal WTY attached to the write command becomes ″ high ″ and the read control signal RDY becomes ″ low ″. As a result, the first clock inverter 30 is positive. ″ High ″ is inputted to the terminal, ″ low ″ which inverts the write control signal WTY at the first inverter 10 is input to the negative terminal, and the second clock inverter 40 is turned ″ low ″ to the positive terminal. ″ Is entered and ″ high ″ is entered at the sub-terminal and turned off.

그러면, 쓰기 어드레스(LA)가 턴온 상태에 있는 제1클럭드 인버터(30)와 제3인버터(50)를 통해 순차적으로 반전되어 도3의 (A)부분처럼 카운터(도면 미도시)로 카운터입력신호(YiT)를 출력한다.Then, the write address LA is sequentially inverted through the first clock inverter 30 and the third inverter 50 in the turned-on state, and the counter inputs to the counter (not shown) as shown in part (A) of FIG. 3. Output the signal YiT.

한편, 도3 (B)부분처럼 읽기제어신호(RDY)에 잡음이 첨가되더라도 각 클럭드 인버터(30,40)가 오프상태에 있을 경우, 카운터(도면 미도시)에 카운터입력신호(YiT)가 입력되지 않게 된다.On the other hand, even when noise is added to the read control signal RDY as shown in FIG. 3B, when the clocked inverters 30 and 40 are in the off state, the counter input signal YiT is applied to the counter (not shown). It will not be entered.

이상에서 설명한 바와 같이 본 발명은 디램에서 외부 어드레스를 입력받아 카운터를 동작할 경우 읽기 명령 혹은 쓰기 명령이 있을 때에서만 카운터의 입력이 각기 개방됨으로써, 불필요한 동작 대기 중에 발생하는 카운터의 오동작 및 전력소모를 방지하는 효과가 있다.As described above, in the present invention, when the counter is operated by receiving an external address from the DRAM, the counter input is opened only when there is a read command or a write command, thereby preventing malfunction and power consumption of the counter generated during an unnecessary operation wait. It is effective to prevent.

Claims (1)

쓰기 명령에 첨부된 쓰기제어신호를 반전하여 출력하는 제1인버터와; 읽기 명령에 첨부된 읽기제어신호를 반전하여 출력하는 제2인버터와; 쓰기제어신호와 상기 제1인버터의 출력에 의해 온/오프 제어되어 쓰기 어드레스를 반전하여 출력하는 제1클럭드 인버터와; 읽기제어신호와 상기 제2인버터의 출력에 의해 온/오프 제어되어, 읽기 어드레스를 반전하여 출력하는 제2클럭드 인버터와; 상기 각 클럭드 인버터의 출력을 반전하여 카운터입력신호로 출력하는 제3인버터로 구성한 것을 특징으로 하는 카운터입력 선택회로.A first inverter for inverting and outputting the write control signal attached to the write command; A second inverter for inverting and outputting the read control signal attached to the read command; A first clock inverter controlled on / off by a write control signal and an output of the first inverter to invert and output a write address; A second clock inverter controlled on / off by a read control signal and an output of the second inverter, and outputting the read address by inverting the read address; And a third inverter for inverting the output of each clocked inverter and outputting the counter input signal as a counter input signal.
KR1019990043478A 1999-10-08 1999-10-08 Circuit for selecting counter input KR20010036453A (en)

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