KR960027352A

KR960027352A - Phase Detection Circuit of Digital Phase Synchronous Loop

Info

Publication number: KR960027352A
Application number: KR1019940040171A
Authority: KR
Inventors: 채희문
Original assignee: 정장호; Lg 정보통신주식회사
Priority date: 1994-12-30
Filing date: 1994-12-30
Publication date: 1996-07-22

Abstract

본 발명은 디지탈 위상동기루프의 위상검출회로에 관한 것이다.The present invention relates to a phase detection circuit of a digital phase locked loop.

종래 위상검출회로는 기준클럭과 변동클럭의 차이가 심할 경우 PLL의 동기되는 시간이 길어지므로 시스템이 불안정해지는 문제점이 있었다.The conventional phase detection circuit has a problem in that the system becomes unstable because the synchronization time of the PLL becomes longer when the difference between the reference clock and the variable clock is severe.

따라서 본발명은 변동클럭과 기준클럭의 위상차가 커서 PLL의 동기되는 시간이 길어지지 않도록 변동클럭과 감시회로가 래치회로를 두어 PLL의 동기시간이 단축되도록 한 것이다.Therefore, in the present invention, the phase difference between the variable clock and the reference clock is large so that the variable clock and the supervisory circuit have a latch circuit so as to shorten the synchronization time of the PLL.

Description

Phase Detection Circuit of Digital Phase Synchronous Loop

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 디지탈 위상동기루프의 위상검출회로 구성도.2 is a block diagram of a phase detection circuit of a digital phase locked loop according to the present invention.

Claims

Phase difference detection means for detecting phase difference by dividing the recording signal and the read signal input to the phase synchronization loop at predetermined periods, and a clock for detecting which of the reference clock and the variable clock is faster by inputting the signal output from the phase difference detection means. And a delay means for delaying the clock as the clock output from the phase difference detection means continues to flow in one direction.

The clock generator of claim 1, wherein the clock difference detection means comprises: a first NAND gate 21 for inverting and outputting the phase difference detection signal output from the phase difference detection means and the signal output from the delay means, and the first NAND gate; A second NAND gate 22 which inversely multiplies the output value of 21 by the delay signal output from the delay means, and outputs the output value of the first NAND gate 21 and the delay signal output from the delay means. A phase detection circuit for a digital phase locked loop, comprising: a first end gate (23) to be multiplied.

2. The apparatus of claim 1, wherein the delay means is configured to logic a third flip-flop (31) for delaying a signal output from the phase difference detecting means by a predetermined period, and a signal and a reset signal output from the third flip-flop (31). The second end gate 32 to be multiplied and the signal output from the second end gate 32 as a reset signal, and the fourth flip flop 33 for delaying a predetermined period as an input signal of the phase difference detecting means. A phase detection circuit of a digital phase locked loop, characterized in that it is configured.

※ Note: The disclosure is based on the initial application.