KR960027323A - Pulse signal transmission circuit - Google Patents

Pulse signal transmission circuit Download PDF

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Publication number
KR960027323A
KR960027323A KR1019940040572A KR19940040572A KR960027323A KR 960027323 A KR960027323 A KR 960027323A KR 1019940040572 A KR1019940040572 A KR 1019940040572A KR 19940040572 A KR19940040572 A KR 19940040572A KR 960027323 A KR960027323 A KR 960027323A
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South Korea
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signal
output terminal
signal transmission
applying
output
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KR1019940040572A
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Korean (ko)
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KR0137694B1 (en
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이재진
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

본 발명은 반도체 소자의 펄스신호 전달회로에 관한 것으로, 입력 펄스폭에 무관하게 일정한 펄스폭을 갖는 출력 펄스폭을 전달하면서 펄스폭이 긴 경우에는 출력신호의 지연신호가 버퍼회로로 유입되지 못하도록 회로를 구현함으로써, 다이렉트 전류(direct current)를 줄이도록 하였다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal transfer circuit of a semiconductor device, wherein an output pulse width having a constant pulse width is transmitted irrespective of an input pulse width, and a delay signal of an output signal does not flow into a buffer circuit when the pulse width is long. By reducing the direct current (direct current) to reduce.

Description

펄스 신호 전달 회로Pulse signal transmission circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 제1실시예에 따른 펄스 신호 전달 회로의 회로도, 제5도는 본 발명의 제2실시예에 따른 펄스 신호 전달 회로의 회로도.4 is a circuit diagram of a pulse signal transmission circuit according to a first embodiment of the present invention, and FIG. 5 is a circuit diagram of a pulse signal transmission circuit according to a second embodiment of the present invention.

Claims (13)

고전위 펄스신호를 전달하는 반도체 소자의 펄스신호 전달회로에 있어서, 신호를 입력하는 입력단자와,상기 입력단자로부터 완충된 신호를 출력하기 위한 제1출력단자와, 상기 제1출력단자의 신호를 일정시간 지연시켜 출력하기 위한 신호지연수단과, 전원전압(Vdd) 및 상기 제1출력단자 사이에 접속되고 상기 신호지연수단으로부터의 출력신호에 의해 상기 제1출력단자로 고전위를 인가하기 위한 제1신호전달 수단과, 상기 제1출력단자 및 접지전압(Vss) 사이에 접속되고 상기 입력신호에 의해 상기 제1출력단자로 저전위를 인가하기 위한 제2신호전달 수단과, 상기 제2신호전달 수단 및 전지전압(Vss) 사이에 접속되고 상기 신호지연 수단으로부터의 출력신호에 의해 상기 제1출력단자로 저전위를 인가하기 위한 제3신호전달수단을 구비하는 것을 특징으로 하는 펄스신호 전달회로.In a pulse signal transfer circuit of a semiconductor device for transmitting a high potential pulse signal, an input terminal for inputting a signal, a first output terminal for outputting a buffered signal from the input terminal, and a signal of the first output terminal A signal delay means for delaying output for a predetermined time and a power supply voltage Vdd and a first output terminal connected between the power supply voltage and the first output terminal for applying a high potential to the first output terminal by an output signal from the signal delay means. A first signal transmission means, second signal transmission means connected between said first output terminal and ground voltage Vss for applying a low potential to said first output terminal by said input signal, and said second signal transmission means A third signal transmission means connected between the means and the battery voltage Vss and for applying a low potential to the first output terminal by an output signal from the signal delay means. A pulse signal transmission circuit for. 제1항에 있어서, 전원전압(Vdd) 및 상기 제1출력단자 사이에 접속되고 상기 입력신호에 의해 상기 제1출력단자에 고전위를 인가하기 위한 제4신호전달수단이 추가로 구비하는 것을 특징으로 하는 펄스신호 전달회로.4. The apparatus of claim 1, further comprising a fourth signal transmission means connected between a power supply voltage Vdd and the first output terminal and configured to apply a high potential to the first output terminal by the input signal. Pulse signal transmission circuit. 제1항에 있어서, 전원전압(Vdd) 및 상기 제2출력단자 사이에 접속되고 상기 상기 제1출력단자에 의해 상기 제2출력단자로 고전위를 인가히기 위한 제5신호전달수단과, 상기 제2출력단자 및 접지전압(Vss) 사이에 접속되고 상기 신호지연수단으로부터의 출력신호에 의해 상기 제2출력단자로 저전위를 인가하기 위한 제6신호 전달수단을 추가로 구비하는 것을 특징으로 하는 펄스신호 전달회로.5. The apparatus of claim 1, further comprising: fifth signal transmitting means connected between a power supply voltage Vdd and the second output terminal for applying a high potential to the second output terminal by the first output terminal; And a sixth signal transmission means connected between the two output terminals and the ground voltage Vss and for applying a low potential to the second output terminal by an output signal from the signal delay means. Signal transmission circuit. 제3항에 있어서, 상기 제2출력단자 및 접지전압(Vss) 사이에 접속되고 상기 제1출력단자에 의해 상기제2출력단자로 저전위를 인가하기 위한 제7신호전달수단을 추가로 구비하는 것을 특징으로 하는 펄스신호 전달회로.4. The apparatus of claim 3, further comprising a seventh signal transmission means connected between the second output terminal and the ground voltage Vss and for applying a low potential to the second output terminal by the first output terminal. Pulse signal transmission circuit, characterized in that. 제1항 내지 제4항에 있어서, 상기 제1, 제4, 제5신호전달수단은 PMOS트랜지스터로 구성되고, 상기 제2, 제3, 제6, 제7신호전달수단은 NMOS트랜지스터로 구성된 것을 특징으로 하는 펄스신호 전달회로.The method of claim 1, wherein the first, fourth, and fifth signal transmission means are configured of a PMOS transistor, and the second, third, sixth, and seventh signal transmission means are configured of an NMOS transistor. Pulse signal transmission circuit characterized in. 제1항에 있어서, 상기 신호지연수단은 직렬로 연결된 두개의 인버터로 구성된 것을 특징으로 하는 펄스신호전달회로.2. The pulse signal transfer circuit according to claim 1, wherein said signal delay means comprises two inverters connected in series. 제1항에 있어서, 상기 제3신호전달수단은 상기 입력신호의 펄스폭이 긴 경우 전원전압(Vdd)이 상기 접지전압(Vss)쪽으로 방전되는 것을 방지하도록 한 것을 특징으로 하는 펄스신호 전달회로.The pulse signal transfer circuit according to claim 1, wherein the third signal transfer means prevents the power supply voltage Vdd from being discharged to the ground voltage Vss when the pulse width of the input signal is long. 저전위 펄스신호를 전달하는 반도체 소자의 펄스신호 전달회로에 있어서, 신호를 입력하는 입력단자와, 상기 입력단자로부터 완충된 신호를 출력하기 위한 제1출력단자와, 상기 제1출력단자의 신호를 일정시간 지연시켜 출력하기 위한 신호지연수단과, 전원전압(Vdd) 및 상기 제1출력단자 사이에 접속되고 상기 입력신호에 의해 제1출력단자로 고전위를 인가하기 위한 제1신호전달수단과, 상기 제1출력단자 및 전지전압(Vss) 사이에 접속되고 상기 신호지연수단으로부터의 출력신호에 상기 제1출력단자로 저전위를 인가하기 위한 제2신호전달 수단과, 상기 전원전압 및 상기 제1신호전달수단 사이에 접속되고 상기 신호지연수단으로부터 출력신호에 의해 상기 제1출력단자로 고전위를 인가하기 위한 제3신호전달수단을 구비하는 것을 특징으로 하는 펄스신호 전달회로.In a pulse signal transfer circuit of a semiconductor device for transmitting a low potential pulse signal, an input terminal for inputting a signal, a first output terminal for outputting a buffered signal from the input terminal, and a signal of the first output terminal A signal delay means for outputting by delaying a predetermined time, a first signal transmission means connected between a power supply voltage Vdd and the first output terminal and applying a high potential to the first output terminal by the input signal; Second signal transmission means connected between said first output terminal and battery voltage Vss for applying a low potential to said first output terminal to an output signal from said signal delay means, said power supply voltage and said first A third signal transmission means connected between the signal transmission means and for applying a high potential to the first output terminal by an output signal from the signal delay means. Call delivery circuit. 제8항에 있어서, 상기 제1출력단자 및 전지전위(Vss) 사이에 접속되고 상기 입력신호에 의해 상기 제1출력단자에 저전위를 인가하기 위한 제4신호전달수단을 추가로 구비한 것을 특징으로 하는 펄스신호 전달회로.9. The apparatus of claim 8, further comprising a fourth signal transfer means connected between the first output terminal and the battery potential Vss and configured to apply a low potential to the first output terminal by the input signal. Pulse signal transmission circuit. 제8항에 있어서, 전원전압(Vdd) 및 제2출력단자 사이에 접속되고 상기 신호지연수단으로부터의 출력신호에 의해 상기 제2출력단자로 고전위를 인가하기 위한 제5신호전달수단과, 상기 제2출력단자 및 접지전압(Vss) 사이에 접속되고 상기 제1출력단자의 신호에 의해 상기 제2출력단자로 저전위를 인가하기 위한 제6신호 전달수단을 추가로 구비한 것을 특징으로 하는 펄스신호 전달회로.9. The apparatus of claim 8, further comprising: fifth signal transmission means connected between a power supply voltage Vdd and a second output terminal for applying a high potential to the second output terminal by an output signal from the signal delay means; And a sixth signal transmission means connected between the second output terminal and the ground voltage (Vss) for applying low potential to the second output terminal by the signal of the first output terminal. Signal transmission circuit. 제10항에 있어서, 상기 제2출력단자 및 접지전압(Vss) 사이에 접속되고 상기 제1출력단자의 신호에 의해 상기 제2출력단자로 저전위를 인가하기 위한 제7신호전달수단을 추가로 구비하는 것을 특징으로 하는 펄스신호 전달회로.11. The apparatus of claim 10, further comprising a seventh signal transmitting means connected between the second output terminal and the ground voltage Vss and applying a low potential to the second output terminal by a signal of the first output terminal. Pulse signal transfer circuit characterized in that it comprises. 제8항 내지 제11항에 있어서, 상기 제1, 제3, 제4, 제5신호전달수단은 PMOS 트랜지스터로 구성되고, 상기 제2, 제6, 제7신호전달수단은 NMOS 트랜지스터로 구성된 것을 특징으로 하는 펄스신호 전달회로.12. The method of claim 8, wherein the first, third, fourth, and fifth signal transfer means are configured of PMOS transistors, and the second, sixth, and seventh signal transfer means are configured of NMOS transistors. Pulse signal transmission circuit characterized in. 제8항에 있어서, 상기 신호지연수단은 직렬로 연결된 두개의 인버터로 구성된 것을 특징으로 하는 펄스신호 전달회로.9. The pulse signal transfer circuit according to claim 8, wherein said signal delay means comprises two inverters connected in series. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040572A 1994-12-31 1994-12-31 Pulse signal transfer circuit KR0137694B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180111498A (en) * 2017-03-31 2018-10-11 미쓰미덴기가부시기가이샤 Battery pack, secondary battery protection integrated circuit, battery monitoring module and data reading method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180111498A (en) * 2017-03-31 2018-10-11 미쓰미덴기가부시기가이샤 Battery pack, secondary battery protection integrated circuit, battery monitoring module and data reading method

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