KR970072694A - Output buffer circuit - Google Patents

Output buffer circuit Download PDF

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Publication number
KR970072694A
KR970072694A KR1019960011960A KR19960011960A KR970072694A KR 970072694 A KR970072694 A KR 970072694A KR 1019960011960 A KR1019960011960 A KR 1019960011960A KR 19960011960 A KR19960011960 A KR 19960011960A KR 970072694 A KR970072694 A KR 970072694A
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KR
South Korea
Prior art keywords
output
signal
buffer circuit
terminal
transistor
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KR1019960011960A
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Korean (ko)
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KR100192583B1 (en
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경계현
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김광호
삼성전자 주식회사
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Priority to KR1019960011960A priority Critical patent/KR100192583B1/en
Publication of KR970072694A publication Critical patent/KR970072694A/en
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Publication of KR100192583B1 publication Critical patent/KR100192583B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

출력버퍼회로에 관한 것이다.Output buffer circuit.

2. 발명이 해결하라고 하는 기술적 과제2. Technical challenges that the invention requires

칩 내부에서 발생된 하이 임피던스를 칩 외부로 전달할 수 있는 출력버퍼회로를 제공함에 있다.And an output buffer circuit capable of transmitting the high impedance generated inside the chip to the outside of the chip.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

칩 내부의 메모리로부터 제공되는 입력신호를 정형하여 외부신호로 출력하기 위한 출력버퍼회로는 상기 입력신호의 레벨상태에 따라 대응되는 제1,2,3 레벨상태의 출력신호를 제1,2출력라인에 제공하는 상태감지회로부와, 상기 제1,2출력라인에 인가되는 신호를 입력으로 하여 상기 해당되는 제1,2,3레벨상태의 출력신호를 출력하는 버퍼회로부를 가짐을 특징으로 한다.An output buffer circuit for shaping an input signal provided from a memory inside the chip and outputting the output signal as an external signal is configured to output output signals of the first, second and third level states corresponding to the level state of the input signal, And a buffer circuit for receiving the signals applied to the first and second output lines and outputting the output signals of the corresponding first, second and third level states.

4. 발명의 중요한 용도4. Important Uses of the Invention

복합화된 메모리에 적합하게 사용된다.It is used suitably for the combined memory.

Description

출력버퍼회로Output buffer circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따라 구성된 출력버퍼회로도, 제3도는 본 발명의 실시예에 따라 구성된 출력버퍼회로도.FIG. 1 is an output buffer circuit diagram constructed in accordance with the present invention; FIG. 3 is an output buffer circuit diagram constructed in accordance with an embodiment of the present invention; FIG.

Claims (6)

칩 내부의 메모리로부터 제공되는 입력신호를 정형하여 외부신호로 출력하기 위한 출력버퍼회로에 있어서; 상기 입력신호의 레벨상태에 따라 대응되는 제1,2,3레벨상태의 출력신호를 제1,2출력라인에 제공하는 상태감지회로부와, 상기 제1,2출력라인에 인가되는 신호를 입력으로 하여 상기 해당되는 제1,2,3레벨상태의 출력신호를 출력하는 버퍼회로부를 가짐을 특징으로 하는 출력버퍼회로.An output buffer circuit for shaping an input signal provided from a memory in a chip and outputting the output signal as an external signal, the output buffer circuit comprising: A state sensing circuit for providing the output signals of the first, second, and third level states corresponding to the level of the input signal to the first and second output lines; And outputting the output signals of the corresponding first, second, and third level states. 제1항에 있어서, 상기 제1,2,3레벨상태의 출력신호는 각기 하이레벨의 신호와 로우레벨의 신호 및 하이임피던스 상태의 신호임을 특징으로 하는 출력버퍼회로.The output buffer circuit according to claim 1, wherein the output signals of the first, second, and third level states are respectively a high level signal, a low level signal, and a high impedance state signal. 제2항에 있어서, 상기 상태감지회로부는 전원전압과 상기 제1출력라인사이에 접속된 제1저항과, 상기 제1출력라인과 상기 입력신호가 입력되는 입력단자사이에 채널이 직렬로 접속되고 상기 전원전압에 게이트단자가 접속된 제1트랜지스터와, 상기 입력단자와 상기 제2출력라인 사이에 채널이 직렬로 접속되고 접지전원사이에 게이트단자가 접속된 제2트랜지스터와, 상기 제2출력라인과 접지전압사이에 접속된 제2저항으로 구성됨을 특징으로 하는 출력버퍼회로.3. The semiconductor memory device according to claim 2, wherein the status sensing circuit part comprises: a first resistor connected between the power supply voltage and the first output line; and a second resistor connected in series between the first output line and an input terminal to which the input signal is input A first transistor having a gate terminal connected to the power supply voltage, a second transistor having a channel connected in series between the input terminal and the second output line and a gate terminal connected between the ground power supply, And a second resistor connected between the output terminal and the ground voltage. 제3항에 있어서, 상기 제1,2트랜지스터는 각기 엔모오스 트랜지스터와 피모오스 트랜지스터임을 특징으로 하는 출력버퍼회로.The output buffer circuit according to claim 3, wherein each of the first and second transistors is an NMOS transistor and a PMOS transistor. 제4항에 있어서, 상기 입력단자에 인가되는 신호가 하이레벨의 신호라면 상기 제1,2출력라인에 인가되는 신호는 로우레벨의 신호가 되고, 상기 입력단자에 인가되는 신호가 로우레벨의 신호라면 상기 제1,2출력라인에 인가되는 신호는 하이레벨의 신호가 되고, 상기 입력단자에 인가되는 신호가 하이 임피던스상태의 신호라면 상기 제1,2출력라인에 인가되는 신호는 각기 하이레벨과 로우레벨의 신호가 되도록 상기 제1,2저항의 크기와 상기 제1,2트랜지스터의 크기를 조절함을 특징으로 하는 출력버퍼회로.5. The method of claim 4, wherein if the signal applied to the input terminal is a high level signal, a signal applied to the first and second output lines is a low level signal, and a signal applied to the input terminal is a low level signal The signal applied to the first and second output lines is a high level signal and if the signal applied to the input terminal is a signal having a high impedance state, And controls the size of the first and second resistors and the size of the first and second transistors so as to be a low level signal. 제1항에 있어서, 상기 버퍼회로부는 전원전압단자와 상기 출력신호가 인가되는 출력단자 사이에 채널이 직렬로 접속되고 상기 제1출력라인에 게이트가 접속된 피모오스 트랜지스터와, 상기 출력단자와 접지전압사이에 채널이 직렬로 접속되고 상기 제2출력라인에 게이트가 접속된 엔모오스 트랜지스터를 가짐을 특징으로 하는 출력버퍼회로.2. The semiconductor memory device according to claim 1, wherein the buffer circuit section comprises: a phyme transistor having a channel connected in series between a power supply voltage terminal and an output terminal to which the output signal is applied and a gate connected to the first output line; And an emmos transistor having a channel connected in series between the voltage and a gate connected to the second output line. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960011960A 1996-04-19 1996-04-19 Output buffer circuit KR100192583B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960011960A KR100192583B1 (en) 1996-04-19 1996-04-19 Output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960011960A KR100192583B1 (en) 1996-04-19 1996-04-19 Output buffer circuit

Publications (2)

Publication Number Publication Date
KR970072694A true KR970072694A (en) 1997-11-07
KR100192583B1 KR100192583B1 (en) 1999-06-15

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KR1019960011960A KR100192583B1 (en) 1996-04-19 1996-04-19 Output buffer circuit

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KR100192583B1 (en) 1999-06-15

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