KR960026796A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device

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Publication number
KR960026796A
KR960026796A KR1019940032803A KR19940032803A KR960026796A KR 960026796 A KR960026796 A KR 960026796A KR 1019940032803 A KR1019940032803 A KR 1019940032803A KR 19940032803 A KR19940032803 A KR 19940032803A KR 960026796 A KR960026796 A KR 960026796A
Authority
KR
South Korea
Prior art keywords
conductive layer
selective growth
forming
layer
insulating layer
Prior art date
Application number
KR1019940032803A
Other languages
Korean (ko)
Inventor
김석수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940032803A priority Critical patent/KR960026796A/en
Publication of KR960026796A publication Critical patent/KR960026796A/en

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Abstract

본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로, 반도체 소자가 고집적화됨에 따라 좁은 면적에서 더욱 많은 정전용량을 필요로하여 저장전극의 표면적을 증가시킴으로써 캐패시터의 정전용량을 극대화하는데 있어서, 반도체기판 상부에 도전층을 형성하고 마스크를 이용한 식각공정과 선택적 성장공정을 이용하여 선택적 성장 절연막을 형성한 다음, 상기 제1감광막패턴을 제거한 후에 상기 선택적 성장 절연막 측벽에 다른 도전층 스페이서를 형성하고 상기 도전층과 다른 도전층이 형성하는 실린더형 구조의 내부에 제2감광막패턴을 형성한 다음, 상기 제2도전층 스페이서를 선택적으로 성장시켜 선택적 성장 도전층을 형성하고 상기 제2감광막을 제거한 다음, 상기 선택적 성장 절연막과 절연막을 제거하여 표면적이 증가된 실린더형 저장전극을 형성함으로써 캐패시터의 정전용량을 증가시킬 수 있어 반도체 소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. As the semiconductor device is highly integrated, it requires more capacitance in a narrow area, thereby increasing the surface area of the storage electrode, thereby maximizing the capacitance of the capacitor. After forming the conductive layer and forming a selective growth insulating layer using an etching process and a selective growth process using a mask, after removing the first photoresist pattern, another conductive layer spacer is formed on the sidewalls of the selective growth insulating layer and the conductive layer and After forming a second photoresist pattern in a cylindrical structure formed by another conductive layer, the second conductive layer spacer is selectively grown to form a selective growth conductive layer, and the second photoresist is removed, and then the selective growth. Cylindrical low with increased surface area by removing insulating film By forming the long electrode, it is possible to increase the capacitance of the capacitor, thereby enabling high integration of semiconductor devices.

Description

반도체소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1F도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 제조공정을 도시한 단면도.1A to 1F are sectional views showing a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.

Claims (7)

반도체기판 상부에 하부절연층을 형성하는 공정과, 상기 하부절연층 상부에 절연막을 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 상기 절연막과 하부절연층을 식각하여 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 반도체기판에 접속되는 제1도전층을 형성하는 공정과, 상기 제1도전층 상부에 제1감광막패턴을 형성하는 공정과, 상기 제1감광막패턴을 이용한 식각공정으로 상기 절연막이 노출되도록 상기 제1도전층을 식각하는 공정과, 상기 노출된 제1절연막을 선택적으로 성장시켜 선택적 성장 절연막을 형성하는 공정과, 상기 제1감광막패턴을 제거하는 공정과, 제2도전층 스페이서를 형성하는 공정과, 상기 제1도전층과 제2도전층 스페이서가 형성하는 실린더형 구조의 내부에만 매립된 제2감광막패턴을 형성하는 공정과, 상기 선택적 성장절연막과 제2감광막패턴 사이에 노출된 제2도전층 스페이서를 선택적으로 성장시켜 선택적 성장 도전층을 형성하는 공정과, 상기 제2감광막패턴을 제거하는 공정과, 상기 선택적 성장 절연막과 절연막을 제거하는 공정을 포함하는 반도체소자의 캐패시터 제조방법.Forming a contact hole by etching the insulating layer and the lower insulating layer by forming a lower insulating layer on the semiconductor substrate, forming an insulating layer on the lower insulating layer, and etching using a contact mask; Forming the first conductive layer connected to the semiconductor substrate through the contact hole, forming a first photosensitive film pattern on the first conductive layer, and etching the first photosensitive film pattern. Etching the first conductive layer to expose the exposed portions, forming a selective growth insulating layer by selectively growing the exposed first insulating layer, removing the first photoresist layer pattern, and a second conductive layer spacer. Forming a second photosensitive film pattern embedded only in a cylindrical structure formed by the first conductive layer and the second conductive layer spacer; Selectively growing a second conductive layer spacer exposed between the selective growth insulating film and the second photoresist pattern to form a selective growth conductive layer; removing the second photoresist pattern; Capacitor manufacturing method of a semiconductor device comprising the step of removing. 제1항에 있어서, 상기 제1감광막패턴은 저장전극마스크를 이용한 식각공정으로 형성된 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the first photoresist pattern is formed by an etching process using a storage electrode mask. 제1항에 있어서, 상기 선택적 성장 절연막 형성공정은 상기 제1감광막패턴을 성장장벽으로 하여 형성된 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the forming of the selective growth insulating layer is performed by using the first photoresist layer as a growth barrier. 제1항에 있어서, 상기 제2감광막패턴은 전체표면상부에 제2감광막을 두껍게 형성하고 산소플라즈마를 이용한 전면식각공정을 실시하여 형성된 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the second photoresist layer pattern is formed by thickly forming a second photoresist layer on an entire surface of the second photoresist layer and performing an entire surface etching process using an oxygen plasma. 제1항에 있어서, 상기 선택적 성장 도전층은 상기 제2감광막패턴과 상기 선택적 성장 절연막을 성장장벽으로 하여 형성된 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the selective growth conductive layer is formed using the second photoresist pattern and the selective growth insulating layer as growth barriers. 제5항에 있어서, 상기 선택적 성장 도전층은 상기 선택적 성장 절연막과 제2감광막패턴의 상부로 과도성장된 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 5, wherein the selective growth conductive layer is overgrown with the selective growth insulating layer and the second photoresist pattern. 제1항에 있어서, 상기 선택적 성장 절연막과 절연막은 상기 제1도전층, 제2도전층 스페이서 및 선택적 성장 도전층과의 식각선택비 차이를 이용하여 제거하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the selective growth insulating layer and the insulating layer are removed using an etch selectivity difference between the first conductive layer, the second conductive layer spacer, and the selective growth conductive layer. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032803A 1994-12-05 1994-12-05 Capacitor Manufacturing Method of Semiconductor Device KR960026796A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940032803A KR960026796A (en) 1994-12-05 1994-12-05 Capacitor Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940032803A KR960026796A (en) 1994-12-05 1994-12-05 Capacitor Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR960026796A true KR960026796A (en) 1996-07-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940032803A KR960026796A (en) 1994-12-05 1994-12-05 Capacitor Manufacturing Method of Semiconductor Device

Country Status (1)

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KR (1) KR960026796A (en)

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