KR960026788A - MOS transistor manufacturing method - Google Patents

MOS transistor manufacturing method Download PDF

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Publication number
KR960026788A
KR960026788A KR1019940035741A KR19940035741A KR960026788A KR 960026788 A KR960026788 A KR 960026788A KR 1019940035741 A KR1019940035741 A KR 1019940035741A KR 19940035741 A KR19940035741 A KR 19940035741A KR 960026788 A KR960026788 A KR 960026788A
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KR
South Korea
Prior art keywords
film
forming
gate
polysilicon
mos transistor
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KR1019940035741A
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Korean (ko)
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KR0167605B1 (en
Inventor
김도우
최국선
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김주용
현대전자산업 주식회사
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Priority to KR1019940035741A priority Critical patent/KR0167605B1/en
Publication of KR960026788A publication Critical patent/KR960026788A/en
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Publication of KR0167605B1 publication Critical patent/KR0167605B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 폴리실리콘 및 실리사이드 막으로 이루어지는 폴리사이드 구조의 게이트 전극을 갖는 모스 트랜지스터 제조방법에 있어서; 반도체 기판상에 게이트 절연막, 게이트용 폴리실리콘막을 증착하고 게이트 마스크를 사용하여 디파인(Define)하는 단계; 산화공정을 실시하는 상기 폴리실리콘막의 표면 일정두께 및 표면상에 산화막을 형성하는 단계; 고농도 불순물 소오스/드레인 영역을 형성하는 단계; 상기 산화막을 제거하는 단계; 저농도 불순물 소오스/드레인 영역을 형성하는 단계; 전체구조 상부에 실리사이드막을 형성하고 게이트 마스크를 사용하여 디파인하는 단계를 포함하는 것을 특징으로 하는 모스 트랜지스터 제조방법에 관한 것으로, 예정된 설계룰과 동일하게 게이트 선폭의 변화없이 게이트를 디파인하여 소자의 동작특성 및 제조수율을 향상시키는 효과가 있다.The present invention provides a MOS transistor manufacturing method having a gate electrode having a polyside structure composed of polysilicon and a silicide film; Depositing a gate insulating film, a polysilicon film for a gate on a semiconductor substrate, and using a gate mask to define the same; Forming an oxide film on the surface and a predetermined thickness of the polysilicon film subjected to an oxidation process; Forming a high concentration impurity source / drain region; Removing the oxide film; Forming a low concentration impurity source / drain region; A method of fabricating a MOS transistor comprising forming a silicide film on an entire structure and using a gate mask to define a MOS transistor. And it has the effect of improving the production yield.

Description

모스 트랜지스터 제조 방법MOS transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 모스 트랜지스터 구조를 나타낸 단면도, 제2A도 내지 제2G도는 본 발명의 일실시예에 따른 트랜지스터 제조공정도.1 is a cross-sectional view showing a conventional MOS transistor structure, Figures 2A to 2G is a transistor manufacturing process according to an embodiment of the present invention.

Claims (3)

폴리실리콘 및 실리사이드막으로 이루어지는 폴리사이드 구조의 게이트 전극을 갖는 모스 트랜지스터 제조방법에 있어서; 반도체 기판상에 게이트 절연막, 게이트용 폴리실리콘막을 증착하고 게이트 마스크를 사용하여 디파인(Define)하는 단계; 산화공정을 실시하는 상기 폴리실리콘막의 표면 일정두께 및 표면상에 산화막을 형성하는 단계; 고농도 불순물 소오스/드레인 영역을 형성하는 단계; 상기 산화막을 제거하는 단계; 저농도 불순물 소오스/드레인 영역을 형성하는 단계; 전체구조 상부에 실리사이드막을 형성하고 게이트 마스크를 사용하여 디파인하는 단계를 포함하는 것을 특징으로 하는 모스 트랜지스터 제조 방법.A MOS transistor manufacturing method having a gate electrode having a polyside structure composed of polysilicon and a silicide film; Depositing a gate insulating film, a polysilicon film for a gate on a semiconductor substrate, and using a gate mask to define the same; Forming an oxide film on the surface and a predetermined thickness of the polysilicon film subjected to an oxidation process; Forming a high concentration impurity source / drain region; Removing the oxide film; Forming a low concentration impurity source / drain region; Forming a silicide film on the entire structure and defining a fine layer by using a gate mask. 제1항에 있어서; 상기 산화공정을 통해 폴리실리콘막 표면상에 형성되는 산화막을 고농도 불순물 소오스/드레인 영역 형성시 이온주입공정을 위해 얇게 식각하는 단계를 더 포함하는 것을 특징으로 하는 모스 트랜지스터 제조 방법.The method of claim 1; And etching the oxide film formed on the surface of the polysilicon film through the oxidation process thinly for the ion implantation process when the high concentration impurity source / drain regions are formed. 제1항에 있어서; 상기 실리사이드막은 텅스텐 실리사이드막인 것을 특징으로 하는 모스 트랜지스터 제조 방법.The method of claim 1; And the silicide film is a tungsten silicide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035741A 1994-12-21 1994-12-21 Mos-transistor fabrication method KR0167605B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940035741A KR0167605B1 (en) 1994-12-21 1994-12-21 Mos-transistor fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035741A KR0167605B1 (en) 1994-12-21 1994-12-21 Mos-transistor fabrication method

Publications (2)

Publication Number Publication Date
KR960026788A true KR960026788A (en) 1996-07-22
KR0167605B1 KR0167605B1 (en) 1999-01-15

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Application Number Title Priority Date Filing Date
KR1019940035741A KR0167605B1 (en) 1994-12-21 1994-12-21 Mos-transistor fabrication method

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KR0167605B1 (en) 1999-01-15

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