KR960016546A

KR960016546A - MPEG Video Playback Device

Info

Publication number: KR960016546A
Application number: KR1019940027987A
Authority: KR
Inventors: 박우석
Original assignee: 이헌조; 엘지전자 주식회사
Priority date: 1994-10-28
Filing date: 1994-10-28
Publication date: 1996-05-22

Abstract

본 발명은 MPEG(앰피이지; Motion Picture Expert Group의 약자이며 화상압축기술명으로 사용됨) 영상재생장치에 관한 것으로서, 특히 엔코더를 사용하여 MPEG 디코더의 압축영상신호 복원동작에 필요한 라스터 클럭(Raster Clock)을 제공함으로 인해 제품의 구성이 간단해진 MPEG 영상 재생장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a video playback apparatus for MPEG (Ampire; abbreviation of Motion Picture Expert Group and used as a picture compression technology name), and in particular, a raster clock required for a compressed video signal recovery operation of an MPEG decoder using an encoder. The present invention relates to an MPEG image reproducing apparatus, which is simplified by providing a product.

압축된 영상신호를 복원하고 화면출력하는데 필요한 신호를 라스터 클록이라 하며, 최소한 27MHz의 LLC(line lock Clock) 신호, 13.5MHz의 CREF(Video Pixel Clock) 신호, HSYNC(수평 동기신호), VSYNC(수직 동기신호)가 필요하게 된다.The signals needed to recover and output compressed video signals are called raster clocks, and at least a 27 MHz LLC (line lock clock) signal, a 13.5 MHz CREF (video pixel clock) signal, HSYNC (horizontal sync signal), and VSYNC ( Vertical synchronization signal).

그러나, 종래의 MPEG 영상재생장치는 MPEG 디코더와 영상처리부의 동작에 필요한 라스터 클록신호의 제공을 위해 제2PLD가 필요하게 되므로 제품의 구성이 복잡해지고, 상기 MPEG 디코더에서 복원된 디지탈 영상신호를 복합영상신호로 출력하기위해 엔코더기능이 추가로 필요하며 엔코더와 MPEG 디코더 그리고, 영상처리부사이의 동기화가 어려운 문제점이 있다.However, the conventional MPEG video reproducing apparatus requires a second PLD to provide a raster clock signal necessary for the operation of the MPEG decoder and the image processing unit, which complicates the configuration of the product and combines the digital video signal reconstructed by the MPEG decoder. In order to output an image signal, an encoder function is additionally required and synchronization between the encoder, the MPEG decoder, and the image processor is difficult.

본 발명은 상기 문제점을 해결하기 위해서 엔코더를 사용하여 MPEG 디코더의 압축영상 신호 복원동작에 필요한 라스터 클륵을 제공함으로 인해 제품의 구성이 간단해진 MPEG 영상 재생장치를 제공함을 목적으로 한다.An object of the present invention is to provide an MPEG video reproducing apparatus, in which a configuration of a product is simplified by providing an raster clock necessary for a compressed video signal reconstruction operation of an MPEG decoder using an encoder.

Description

MPEG Video Playback Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명 MPEG 영상 재생장치의 블럭도,3 is a block diagram of an MPEG video reproducing apparatus of the present invention;

제4도는 본 발명 엔코더부의 블럭도.4 is a block diagram of an encoder unit of the present invention.

Claims

PLD 21 which decodes various addresses input / output via PC bus and supplies raster clock signal output from encoder 28 to image processor 30 and MPEG decoder 22, and from PC bus An address latch for designating an address of an MPEG register 22 for restoring a compressed video signal to an original video signal and an internal register of the MPEG decoder 22 in which a compressed video signal input to the MPEG decoder 22 is to be stored (23), a control register (24) which stores a constant program for controlling the MPEG decoder (22) and the encoder section (28), and a state register (25) for reading the operating state of the MPEG decoder (22). ), A RAM 26 for temporarily storing a compressed video signal for the MPEG decoder 22 to restore, a 16-bit luminance signal Y and a color difference signal U, which are restored in the MPEG decoder 22. A multiplexer 27 for converting V) to 8 bits, and the multiplexer Encoder 28 converts the luminance signal and the color difference signal output from the document 27 into a composite video signal, and outputs a raster clock signal for the composite video signal to the PLD 21 and pixel data from the VGA. And a connector 29 for receiving synchronization information, and an image processor 30 reconstructing the image signal restored by the MPEG decoder 22 according to the raster clock signal output from the PLD 21 and outputting the frame unit in frame units. And a frame buffer 31 for temporarily storing the video signal output from the image processor 30 in units of frames one frame at a time, and converting the video signal output from the frame buffer 31 into an analog signal and then converting the image signal into a VGA. An MPEG image playback apparatus comprising: a D / A converter 32 for mixing with input analog R, G, and B data and outputting it to a monitor.

The data processing unit of claim 1, wherein the encoder unit 28 supplies an 8-bit luminance signal and a color difference signal output from the multiplexer 27 to the encoder 37, and the image processor 30. A control interface 34 for supplying the control signals SC1, SDA, and SA inputted through the I2C bus to each part, an oscillator 35 for oscillating a clock signal of a predetermined frequency (27 MHz), and the oscillator 35 The clock generator 36 generates and outputs a raster clock signal with a clock signal having a constant frequency output from the clock signal, and the clock generator 36 outputs an 8-bit image signal input from the data interface 33. The encoder 37 converts and outputs the composite video signal according to the raster clock signal, and the D / A converter 38 converts the composite video signal, which is a digital signal output from the encoder 37, into an analog signal. Characteristic ampere (M PEG) image playback device.

2. The decoder of claim 1, wherein the decoder 22 is inputted by data and an address latch 23 input through a 16-bit data line according to a control signal of a PLD 21 supplied with a predetermined program from the control register 24. An MPEG video reproducing apparatus, wherein an internal register of the decoder 22 is initialized by a 20-bit address.

The amplifier (MPEG) according to claim 2, wherein the encoder (37) is configured to initialize an internal register of the encoder (37) by the control signals (SC1, SDA, SA) output from the control interface (34). Video playback device.

※ Note: The disclosure is based on the initial application.