KR100678355B1 - Image display and control device and its method - Google Patents

Abstract

The present invention relates to an image display and control apparatus for displaying a computer graphics image of square pixels in a regular roundness in the MPEG2 image format of a rectangular pixel. The graphics processor block generates data of 640 x 480 pixels, two-line data stored in two 1H buffers, and multiplies each of the weights output by the weight control circuit through the line conversion circuit. As a result, data of 640 × 432 is generated. The delay circuit delays the vertical sync signal output by the graphics processor block by 14H. The phase comparator circuit compares the vertical synchronization signal whose phase is 14H delayed with the vertical synchronization signal output by the MPEG2 video decoder. The generation timing of the vertical synchronization signal in the graphics processor block is set to be about 14H faster than the generation timing of the vertical synchronization signal of the MPEG2 video decoder. The memory capacity required for the buffer before the line conversion circuit in the processing circuit is sufficient for two lines, while the line conversion processing is executed without breaking the pixel data.

Description

Video display and control device and his method

1. Field of invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display and control apparatus and a method thereof, and more particularly, to a second display having an aspect ratio, wherein an image having one aspect ratio consists of pixels having a rectangular shape and having another aspect ratio. The present invention relates to an image display and control device and a method of ensuring roundness when displayed as an image.

2. Description of related technology

Home television receivers or display monitors (NTSC television CRT display monitors, hereinafter simply called TV monitors) have a large dot pitch and a slow screen refresh rate (30 frames per second). If it is desired to display a graphics image generated on a personal computer on a TV monitor, the displayed image is coarser than the corresponding image on the display monitor of the personal computer. Therefore, the proper picture cannot be reproduced on the TV monitor.

If the TV monitor installed in the living room may possibly display a graphics image generated by a personal computer, both the television image and the computer graphics image may be provided using the same monitor. For this purpose, a VGA / NTSC scan converter is used. The scan converter initially records the image data supplied by the personal computer on the frame memory, reads the image data at the vertical synchronizing frequency of the television receiver, and converts the image data into a composite image signal to be displayed on a TV monitor.

If a scan converter with frame memory is built into the personal computer, the overall cost of the personal computer will be increased.

In addition, a personal computer may be equipped with a DVD (Digital Versatile Disc) player. The DVD player plays back the bit stream in the MPEG (Moving Picture Expert Group) 2 format and the reproduced data is decoded through an MPEG2 decoder to be displayed on a TV monitor.

In the above methods, if the graphics image produced on the personal computer is duplicated on the image read by the MPEG2 decoder (referred to as MPEG2 image), the following problem will occur.

Digital coding rules for composite signals in current television systems are recommended in the ITU-R (International Telecommunication Union Radio Communication Sector) BT. Formulated as 601. This recommendation specifies the sampling frequency, quantization level, etc. in the conversion of luminance and chrominance analog signals to digital signals.

ITU-R BT. According to 601, the sampling frequency is 13.5 MHz and the number of effective pixels for the luminance signal per scan line is 720. The NTSC standard, on the other hand, specifies that a frame consists of 525 lines. From these, the number of effective lines actually shown on the screen is about 480.

According to MP @ ML (MainProfile @ Main Level), MPEG2, 720 pixels / line, 576 lines / of international standard ISO / ITC (International Organization for Standardization / International Electrotechnical Commission) 13818 The frame and 30 frames / second are specified.

An MPEG2 image is composed of pixel data of 720 x 480 dots. In addition, the MPEG2 decoder outputs odd field image data composed of 720 × 240 dots and even field image data composed of 720 × 240 dots in an interlaced scanning system having a speed of 60 fields per second. Thus, an MPEG2 image of 720 x 480 dots is displayed at a rate of 30 frames per second. Each dot constituting an image on the screen is called a picture element or pixel.

When an MPEG2 image of 720 x 480 pixels (with an aspect ratio of 3: 2) is displayed on a TV monitor with an aspect ratio of 4: 3, the image is a rectangle in which the longer side of each pixel is vertically oriented. It is displayed on the screen to appear as a pixel.

Not all 720 × 480 pixels in the MPEG2 picture appear on the TV monitor, and approximately 10% overscan area is provided in each vertical and horizontal directions. In fact, what you see on the screen is about 648 x 432 pixels. 12A shows the interrelationship between the visible area and the image-displayed but invisible area (overscan area).

Computer graphics images according to the well-known VGA (Video Graphics Array) formulated by IBM as a graphics standard for IBM PC AT and their compatible machines include 640 x 480 pixels in one frame. As shown in FIG. 12B, a VGA image is displayed on the screen such that all pixels are visible on the display monitor.

When a VGA image is displayed on a TV monitor having an aspect ratio of 4: 3, each pixel is displayed as a square pixel because the image of 640x480 pixels constituting the VGA image is a 4: 3 aspect image correspondingly.

As illustrated in FIG. 11, when an MPEG2 image of 720 × 480 pixels displayed on a TV monitor is combined with a VGA image of 640 × 480 pixels in a redundant form, the VGA image is vertically extended due to a difference in aspect ratio. That is, the roundness of the image is not one.

Referring to FIG. 13, a VGA image of 640 × 480 pixels is line-converted from 480 lines to 432 lines so that the VGA image has an aspect ratio of 4: 3 that is the same as that of the MPEG2 image, and is synthesized with the MPEG2 image. In this way, the VGA image is displayed as a normal sphere.

If a VGA image is displayed after conversion from 480 lines to 432 lines, the number of lines should be bisected by 216 to be compatible with the interlaced scanning system.

Referring to FIG. 14, the removal of the top 12 lines and the bottom 12 lines from one field MPEG2 image of 240 lines produces 216 lines, and one field VGA image is displayed over 216 lines in an interlaced scanning system. If it does, the VGA picture will overlap the normal sphere on the MPEG2 picture.

These 216 lines are generated by processing the image data of the lines in the vicinity of 480 lines of the VGA image in an interlaced scanning system. If scanning of an interlaced VGA image is performed at twice the refresh rate of the NTSC scheme, the interlaced VGA image is scanned at a rate of 480 lines per field. An interlaced VGA image of 216 lines per field may be obtained by processing 480 lines of interlaced VGA image.

As shown in FIG. 14, lines in the region of r of 216 lines in the interlaced VGA image may be generated from lines in the region R of 480 lines in the interlaced VGA image. As can be seen in FIG. 14, at the timing of generating the lines in the region r, the lines in the region R have not yet been supplied. For this reason, the non-interlaced VGA image is stored once in the frame memory, exiting from the stored image, and the image data corresponding to the lines in the area are read out to produce the lines of the interlaced VGA image.

The use of frame memory to convert line numbers adds to the cost of the device.

Summary of the Invention

Accordingly, it is an object of the present invention to provide an image display and control apparatus which displays computer graphics images on a TV monitor in a low-cost and normal sphere.

According to a first aspect of the present invention, an image display and control device for displaying a first image having a first aspect ratio as a second image having a second aspect ratio stores pixel data of the first image in horizontal line units. A number of lines for converting the number of lines including one display image of the first image to process image data of at least two lines stored in the memory means and to display the first image at the second aspect ratio Converter means and timing control means for controlling the timing of the storage operation of the memory means such that the first image is not broken in the conversion process by the line number converter means.

According to a second aspect of the present invention, in an image display and control method for displaying a first image having a first aspect ratio as a second image having a second aspect ratio, the method includes the pixel data of the first image in horizontal line units. And a display image of one of the first images to process the image data of at least two lines stored in the storing step to display the first image at the second aspect ratio. And controls the storage operation timing of the storage step so that the first image is not broken in the conversion step.

In the image display and control apparatus and method thereof according to the first and second aspects of the present invention, the image data of at least two lines may be configured to include: It is processed to convert the number. Since a memory capacity as large as that for storing image data for at least two lines is sufficient, a low cost design is achieved.

Description of the Preferred Embodiments

1 shows an example of an AV (audio-video) system incorporating an image display and control device of the present invention. As shown, a personal computer 1 is connected to a television receiver 3 together with an AV device 2 comprising a tuner, an amplifier and a video disc player. The television receiver 3 includes a CRT 4 for displaying an image and a loudspeaker 5 for outputting a sound.

The keyboard 11 comprises a plurality of keys 12 and a touchpad 13 and an infrared signal corresponding to the operation of each key from the infrared transmitter 14 of the keyboard to the personal computer 1. It is designed to emit.

2 is an external view of a personal computer 1. The dimensions of the personal computer 1 are 225 mm wide x 94 mm high x 350 mm deep. The personal computer 1 is provided with flip-down doors 21 and panels 22 on both sides of the door 21. Positioned on the left panel in FIG. 2 is an infrared ray for receiving infrared signals emitted by the infrared transmitter 14 at the power switch 23 and keyboard 11 for turning the power on or off. Receiver 24.

The personal computer 1 has, on its upper surface, socket portions 25 for receiving the feet of the peripheral device so that it is reliably located in the personal computer 1 when the peripheral device is interfaced.

3 shows a state in which the door 21 of the personal computer 1 is opened. With the door open as shown, the DVD (digital universal disk) drive 33 is shown. Arranged below the DVD drive 33 are USB terminals 31 and 1394 terminals 32 conforming to the IEEE (Electrical and Electronic Engineers Association) 1394 standard as a series of connectors.

4 shows a state in which the rear door 41 of the personal computer 1 is opened. With the door 41 open, the PC card slot 42 is shown. Arranged below the PC card slot 42 are a printer terminal 45 connected to the printer and a VGA terminal 46 for outputting computer graphics data, as well as a USB terminal 43 and a 1394 terminal 44.

5 is a block diagram of the internal structure of the personal computer 1. The CPU (central processing unit) 71 may be, for example, a Pentium processor (trade name) manufactured by Intel Corporation. The CPU operates under its internal clock 166 MHZ or external clock 66 MHZ. The RAM 72 is a 16 MB main memory device and suitably stores programs and data executed by the CPU 71. ROM 73 stores programs executed by CPU 71 to execute various processes. Electrically erasable programmable read only memory (EEPROM) 74 stores data that needs to be stored as needed, even when power is removed from the personal computer 1.

Graphics processor block 75 includes moving image processing (including color space conversion for converting YUU signal from graphics signal data format to RGB signal in moving image data format and scaling (enlargement or reduction) for representing an image in a desired size. , Three-dimensional graphics processes (rasterization for projecting three-dimensional objects onto a two-dimensional plane, gourd shading processing to achieve an object with a smoother look) Gouraud shading processes and alpha-blending processes for displaying translucent objects are executed, and the results of these processes are written to video memory 76 and output to synthesizer circuit 85.

The MPEG2 video decoder 77 decodes the data reproduced from the DVD by the DVD drive 33 and outputs the decoded data to the synthesizer circuit 85. The digital sound processor block 81 expands the ADPCM (Adaptive Difference Pulse Code Modulation) sound, expands the MPEG audio data, the frequency-modulated sound and the reverberation ( That is, the sound is synthesized by a special effect sound for generating an audio signal by synthesizing a plurality of sine waves having different frequencies and amplitudes, and a MIDI (Musical Instrument Digital Interface) wave table Synthesize them. Synthesizing a MIDI wave table is for reproducing MIDI data using a built-in synthesizer based on a wave table that stores digital data that is a sound component of each musical device. Thus, the separately processed audio signals are synthesized by a built-in audio synthesizer, converted into analog audio signals, and output as sound through the loudspeaker 5 of the television receiver 3.

An Intercast (TM) substrate 78 is used to receive and demodulate the intercast broadcast signal through the antenna 91. In intercast broadcasting, HTML (Hyper Text Markup Language) data, which serves as the basis for the World Wide Web (WWW) page, is stored in the vertical retrace period before transmission. Is inserted. The received data is stored in a hard disk driven by a hard disk drive (HDD) 80. By roaming HTML data on hard disk drive 80, the operator obtains a pseudo-interactive environment.

More specifically, scores and image clips that are still pictures of dramatic moments can be broadcast, for example, in an intercast of sports programs. Still pictures and video clips can be linked to associated information and can be accessed to obtain such associated information from a source linked via a telephone line. Intercast was developed by Intel.

The DSVD (Digital Simultaneous Voice and Data) modem 79 is a DSVD scheme developed by Intel Corporation. The DSVD modem 79 time-division multiplexes the voice and data, transmits the voice and data over the telephone line through the modular jack 92, and converts the DSVD signal input through the telephone line into the voice signal and Demodulate and separate data. In this method, digitally compressed speech signals and conventional speech signals are multiplexed using the V.43 protocol header. The maximum transmission rate is 28.8 kbit / sec when no voice signal is present, and the maximum transmission rate is 19.2 kbit / sec when voice signal is present. The transmission speed of the voice signal is 9.6 kbit / second. The compression and decompression method of the voice signal may be DitiTalk (trade name) by Rockwell or TrueSpeech (trade name) by DSP group.

The keyboard controller 84 receives a signal from the infrared receiver 24 and supplies a signal corresponding to the received signal to the CPU 71.

The synthesizer circuit 85 synthesizes the output of the graphics processor block 75 and the output of the MPEG2 video decoder 77 and supplies the synthesized signal to the NTSC encoder 86 as needed. NTSC encoder 86 converts the video data supplied by synthesizer circuit 85 into an NTSC analog video signal, which is supplied to television receiver 3.

Figure 3 shows only one bus for convenience, but in practice the bus is a local bus that connects the CPU 71 to the RAM 72, an ISA (industry standard architecture) connected to the keyboard controller 84. Architecture) bus and Peripheral Component Interconnect (PCI) bus for ROM 73, HDD 80, and the like. The ISA bus is an 8-bit bus or a 16-bit bus, while the PCI bus is a 32-bit or 64-bit bus. The PCI bus runs at speeds between 25 MHz and 66 MHz and provides throughput of 528 KB / second. This speed is 42 times higher than that of the ISA bus.

Expansion slot 82 is for the PCI bus and expansion slot S3 is for the ISA bus. The necessary functionality can be added by connecting peripheral circuitry (eg SCSI boards).

Dedicated bus bridge circuits (not shown) are arranged between the local bus and the PCI bus and between the PCI bus and the ISA bus, respectively.

6 is a block diagram of the synthesizer circuit 85. The vertical sync signal Vsync output by the graphics processor block 75 is delayed by 14H (14 lines) by the delay circuit 101 and then supplied to the phase comparator circuit (PC) 102. The delay circuit 101 is provided with a horizontal sync signal Hsync by the graphics processor block 75 to provide a delay time of 14H.

The phase comparator circuit 102 is provided with a vertical synchronization signal output by the MPEG2 video decoder 77. The phase comparator circuit 102 compares the vertical sync signal supplied by the graphics processor block 75 through the delay circuit 101 with the vertical sync signal supplied by the MPEG2 video decoder 77 to compare the phase error between the two. Output to voltage-controlled oscillator (VCO) 103. In response to the phase error supplied by the phase comparator circuit 102, the voltage-controlled oscillator 103 generates a phase clock and outputs it to the graphics processor block 75.

The write control circuit 104 generates a write control signal in synchronization with the horizontal synchronizing signal supplied by the graphics processor block 75 to direct the write signal to the 1H buffers 131, 132, and 134 of the processing circuit 105B. Output it. The read control circuit 106 generates a read control signal in synchronization with the horizontal signal supplied by the MPEG2 video decoder 77 to direct the read control signal to the 1H buffers 131, 132, and 134 of the processing circuit 105B. Output it.

The line counter 107 counts the horizontal synchronizing signal output by the MPEG2 video decoder 77, and the counted reading control circuit 106, the weight control circuit 110, and the key generator circuit. Output to (109). The pixel counter 108 counts the pixel clock PixCLK output by the MPEG2 video decoder 77 and outputs this count to the key generator circuit 109.

The weight control circuit 110 generates a weight for the count provided by the line counter 107 and outputs the weight to the line conversion circuit 133 of the processing circuit 105B. The key generator circuit 109 defaults to values of 40 pixels (dots) and 24 lines as reference values. When the count from the pixel counter 108 and the count from the line counter 107 become a premeasured correlation with respect to the default reference values, the key generator circuit 109 multiplexes the premeasured key signal with a multiplexer 111. )

In the processing circuit 105B, the 1H buffer 131 and the 1H buffer 132 store blue pixel data for one line 1H output by the graphics processor block 75 and store the stored data. Output to the line conversion circuit 133. In response to the weight supplied by the weight control circuit 110, the line conversion circuit 133 processes data from the 1H buffer 131 and the 1H buffer 132, and transfers the processed data to the 1H buffer 134. Output it. Data read from the 1H buffer 134 is supplied to the multiplexer 111.

The synthesizer circuit also includes processing circuits 105R and 105G that process red and green pixel data, respectively, in addition to processing circuit 105B that processes blue pixel data. These circuits have the same circuit arrangement as that of the circuit of the processing circuit 105B.

The multiplexer 111 converts the R, G and B data for the VGA image from the processing circuits 105R, 105G and 105B and the graphics processor block 75 into the R, G and B data from the MPEG2 video decoder 77. And the synthesized data are output to the NTSC decoder 86.

7 shows the internal structure of the keyboard 11. The detector circuit 141 detects which of the keys 12 operates. The detector circuit 141 also detects the coordinates (X, Y) of the activated point on the contact pad 13. The detector circuit 141 outputs the detected results to the transmitter module 142. The transmitter module 142 converts an input signal into a transmission signal and then supplies it to the infrared transmitter 14 to be transmitted as an infrared signal.

The battery 143 supplies power to the power supply circuit 144. The power supply circuit 144 supplies power required for the detector circuit 141 and the transmitter module 142. The power switch 145 is operated to start or stop using the keyboard 11.

The operation of the device is now described. For example, to play a DVD, the user opens the door 21 of the personal computer 1 and loads a DVD (not shown) into the DVD drive 33. The user operates the power switch 145 for the keyboard 11 to power the keyboard 11 and the necessary keys of the keys 12 to instruct the DVD drive to play the DVD.

The detector circuit 141 receives a signal from the activated key 12 and outputs the detected signal to the transmitter module 142 in response to the key 12. The transmitter module 142 converts the detected signal into a transmission signal, which is then transmitted by the infrared transmitter 14 to the personal computer 1 as an infrared signal.

The personal computer 1 receives an infrared signal at its infrared receiver 24. Upon detecting the signal output of the infrared receiver 24, the keyboard controller 84 outputs signals to the CPU 71 in response to the detected signal. In response to the input signal, the CPU 71 controls the DVD drive 33 and starts playback of the DVD.

Video data from data reproduced from the DVD is supplied from the DVD drive 33 to the MPEG2 video decoder 77 and decoded there. Data output by the MPEG2 video decoder 77 is supplied to the NTSC encoder 86 through the multiplexer 111 of the synthesizer circuit 85. NTSC encoder 86 converts the input data into an analog NTSC signal and outputs it to television receiver 3 (TV monitor) so that it is displayed on CRT 4. In this way, an MPEG2 image of 720 × 480 rectangular shaped pixels is provided in a normal sphere.

Audio data from data reproduced from the DVD is input from the DVD drive 33 to the digital sound processor block 81 and decoded there. The decoded data is output to the loudspeaker 5 of the television receiver 3 in which D / A conversion and sound are emitted.

In this way, the user enjoys the programs recorded on the DVD using the television receiver 3.

To play the computer graphics image, the user also operates the keyboard 11. In the same way as above, the infrared type command is input from the keyboard 11 to the personal computer 1. In response to the command, the CPU 71 controls the graphics processor block 75 to generate VGA image data in a 640 × 480 pixel format. R, G, and B data of the VGA image output by the graphics processor block 75 are supplied to the processing circuits 105R, 105G, and 105B, respectively.

The processing circuit 105B operates as follows. Since the processing circuits 105R and 105G are operated in the same manner as the processing circuit 105B, only the operation of the processing circuit 105B will be described herein.

The pixel data for the first line L ₁ of blue pixel data output by the graphics processor block 75 is stored in the 1H buffer 131. When the pixel data for the next line L ₂ is output, it is stored in the 1H buffer 131. Pixel data for the previously stored line L ₁ is sent to the 1H buffer 132. In the same way, the third line data, then L ₃ , L ₄ . Are continuously stored in the 1H buffers 131 and 132.

The line conversion circuit 133 multiplies the two suitable data supplied by the 1H buffers 131 and 132 with the weights w ₁ and w ₂ supplied by the weight control circuit 110 to sum these results. Get the line ML _i . These weights w ₁ , w ₂ vary as shown in FIG. 8.

More specifically, as shown in FIG. 8, pixel data for the line L ₁ output by the 1H buffer 132 is multiplied by 0.9 as the weight w ₁ and the line L ₂ output by the 1H buffer 131 is multiplied. The pixel data for is multiplied by 0.1 as the weight w ₂ . The output ML ₁ of the line conversion circuit 133 is 0.9 L ₁ + 0.1 L ₂ .

When the 1H buffer 132 outputs line L ₂ and the 1H buffer 131 outputs line L ₃ , the weights W ₁ , W ₂ are 0.8 and 0.2, respectively. Therefore, the output ML ₂ of the line conversion circuit 133 is 0.8 L ₂ + 0.2 L ₃ .

In the same manner as above, the weight w ₁ decreases by 0.1 for each line and the weight w ₂ increases by 0.1 for each line. 9 lines ML ₁ to ML ₉ are driven from lines L ₁ to L ₁₀ . In the method shown in Fig. 8, the same step is repeated every 10 lines. In this way, 432 (= 480 x 9/10) lines are generated from the 480 lines in the graphics image.

Of the data for the 432 lines output by the line conversion circuit 133, odd-numbered lines ML ₁ , ML ₃ , ML ₅ , ML ₇ ,. Data for a total of 216 lines is written onto the next stage 1H buffer 134 in the odd field. In the even field, even-numbered lines ML ₂ , ML ₄ , ML ₆ , ML ₈ ,... The data for a total of 216 lines is recorded on the 1H buffer 134. That is, interlaced VGA image data is converted to interlaced data.

In each field, 216 lines of data read from the 1H buffer 134 are input to the multiplexer 111. The multiplexer 111, when supplied by the MPEG2 video decoder 77 before supplying the data to the NTSC encoder 86, duplicates the data on the data of the MPEG2 video. When no MPEG2 video is supplied, the multiplexer 111 feeds data directly from the 1H buffer 134 to the NTSC encoder 86. As already described, the NTSC encoder 86 converts the input data into an NTSC signal and outputs it to the television receiver 3 for display on the CRT 4.

In the MPEG2 field shown in Fig. 9, 240 lines are arranged except 14 lines after one vertical sync signal and 14 lines before the next vertical sync signal, while 216 lines in one field in an interlaced VGA scanning system are MPEG2. The first 12 lines and the last 12 lines from the 240 lines of the image are removed and arranged. The key generator circuit 109 controls when the count of the key generator circuit 109 (indicating the number of lines in the MPEG2 image) is in the range of 0 to 12, that is, within half of the default reference value 24 and in the range of 229 to 240. Gives an unsigned signal. When the count is in the range of 13 to 228, the key generator circuit 109 outputs its control signal to the multiplexer 111. When the multiplexer 111 receives a control signal from the key generator circuit 109, the multiplexer 111 outputs the interlaced VGA image data supplied from the processing circuits 105R, 105G, and 105B to the NTSC encoder 86. .

Since the number of pixels per line in the VGA image is 640 as shown in FIG. 13, pixel data corresponding to the VGA image does not exist at the timings of the first 40 pixels and the last 40 pixels of the 720 pixels constituting the MPEG2 image. Do not. The key generator circuit 109 does not provide control signals when the counter of the pixel counter 108 (which indicates the number of pixels for each line in the MPEG2 image) is in the range of up to 40 and in the range of 641 or more. The key generator circuit 109 provides a control signal when the counter is in the range of 41 to 680. In response to a control signal, the multiplexer 111 supplies pixel data for 640 VGA pixels on each horizontal scan to NTSC encoder 86.

As already described with reference to FIG. 8, the processing circuits 105R, 105G and 105B require collecting data on two lines L ₄₇₉ , L ₄₈₀ in advance to drive the new line L ₄₃₂ . do. However, as shown in FIG. 6, the processing circuits 105R, 105G, and 105B are not provided with frame memories. Only 1H buffers 131, 132 for two lines are provided before the line conversion circuit 133. In the embodiment shown in FIG. 6, the timing of generation of the vertical sync signal of the interlaced VGA in the graphics processor block 75 is set to be 14 lines earlier than the timing of the generation of the vertical sync signal in the interlaced MPEG2 image. The last line of 480 lines in the interlaced VGA image is supplied at a timing two lines earlier than the timing of the last line of 216 lines in the interlaced VGA image.

As a result, the synthesizer circuit 85 shown in FIG. 6 causes the delay circuit 101 to delay the vertical synchronization signal of the VGA image output by the graphics processor block 75 by 14 lines, and delay the delayed signal to a phase comparator. Supply to circuit 102. Phase comparator circuit 102 creates a delayed vertical sync signal, delayed by 14 lines from the signal supplied by graphics processor block 75, and generates a phase error signal that synchronizes with the vertical sync signal in the MPEG2 image. As shown in Fig. 9, the timing of generation of the vertical synchronization signal generated by the graphics processor block 75 is thus 14 lines faster than the vertical synchronization signal generated by the MPEG2 video decoder 77.

At the timing that the processing circuit 105B outputs the last line ML ₄₃₁ of the 216 lines of the odd field (or the last line ML ₄₃₂ of the 216 lines of the even field), the 1H buffers 131 and 132 are respectively the lines L ₄₇₉ and Hold L ₄₈₀ . The line conversion circuit 133 prevents the failure of the line number conversion processing (failure to generate the line ML _i ) due to lack of data, and performs the line number conversion on a real-time basis.

In this embodiment, the delay circuit 101 adjusts the timings of the vertical synchronization signals from the graphics processor block 75 and the MPEG2 video decoder 77. Alternatively, the parameters in register CRTC (CRT controller) of graphics processor block 75, where various parameters are set, read 14 lines of timing for the vertical synchronization signal in synchronization with the clock supplied by voltage-controlled oscillator 103. It can be set to internally generate a vertical synchronization signal having a.

Fig. 10 shows embodiments of the display on the television receiver 3, the MPEG2 image output by the MPEG2 video decoder 77 is displayed on the A area of the CRT 4 in the form of a moving picture. Displayed on the area B is a window displayed by the application software for the facsimile receiver under CPU 71 control during the facsimile reception time. The current window displays the message FAX RECEIVED.

Area C provides an icon that can be clicked to launch the telephone transmit / receive software. Area D provides an icon that can be clicked to open a window that provides a folder or file in a directory on the computer. The E area provides an insertion screen (reduced screen) for displaying a television picture received through the intercast substrate 78 in a picture-in-picture format. Indications of areas B through E are all generated and provided in graphics processor block 75. These images for these areas are provided in a normal sphere.

In the above embodiment, the graphics image consists of 640 × 480 pixels, while the MPEG2 image consists of 720 × 480 pixels. The number of pixels is not limited to these numbers. Aspect ratios are not limited to those described above.

In the image display and control apparatus and the method thereof according to each of the first and second embodiments of the present invention, pixel data for line number conversion is stored on a line by a line basis, and the first image is a normal spherical shape as a second image. Is displayed.

The present invention provides an image display and control device which is low in cost and displays a computer graphics image on a TV monitor in a normal sphere.

1 is a perspective view of an audio visual (AV) system incorporating an image display and control device of the present invention.

2 is a front perspective view of the personal computer shown in FIG.

3 is a perspective view of the personal computer of FIG. 2 with the door open;

4 is a perspective view of the rear door of the personal computer in an open state.

5 is a block diagram of the internal structure of the personal computer of FIG.

6 is a block diagram of the synthesizer circuit shown in FIG.

7 is a block diagram of the internal structure of the keyboard shown in FIG.

8 is an explanatory diagram showing line number conversion processing;

9 is an explanatory diagram showing timings of a vertical synchronizing signal of an MPEG2 image and a vertical synchronizing signal of a VGA image;

10 is a diagram showing examples of a graphics video and an MPEG2 video.

11 is an explanatory diagram of aspect ratios of MPEG2 video and VAG video;

12 is an explanatory diagram showing display regions of a graphics image and a television image;

Fig. 13 is a diagram showing the principle of combining MPEG2 video and VGA video into a normal sphere.

14 is an explanatory diagram showing timings of vertical synchronization signals of MPEG2 video and VGA video;

* Explanation of symbols for main parts of drawings *

1. Personal computer 2. AV device

3. Television receiver 4. CRT

5. Loudspeaker 11. Keyboard

12. Key 13. Contact pad

14. infrared transmitter

Claims (12)

An image display and control device for displaying a first image having a first aspect ratio as a second image having a second aspect ratio, the apparatus comprising: Memory means for storing pixel data of the first image in units of horizontal lines; A line number converter means for processing the pixel data of at least two lines stored in the memory means and converting the number of lines including one display image of the first image to display the first image at the second aspect ratio; And timing controller means for controlling a storage operation timing of the memory means such that the first image is not broken in the conversion process by the line number converter means. The image display and control apparatus according to claim 1, wherein the timing controller means controls the storage operation in units of horizontal lines such that the line form of pixel data read from the memory means is a line format of an interlaced scanning system. The method of claim 2, wherein the first image comprises 480 lines of an interlaced scanning system, The second image comprises 480 lines of an interlaced scanning system, The memory means stores pixel data for two lines, The line number converter means processes the pixel data for two lines to convert 480 lines to 432 lines, And the timing controller means controls the start timing of the first image to be 14 lines earlier than the start timing of the second image. The image display according to claim 1, further comprising pixel data synthesizer means for synthesizing the pixel data of the first image and the pixel data of the second image having the number of lines converted by the line number converter means. controller. 2. The apparatus of claim 1, further comprising signal image synthesizer means for synthesizing pixel data of the second image and pixel data of the first image having the number of lines converted by the line number converter. And the pixel data of is read out horizontally from the memory means in a line form of an interlaced scanning system. 6. The image display and control apparatus according to claim 5, wherein the first image is a computer graphics image including pixels of square shape, and the second image is an MPEG format image including pixels of rectangular shape. A method of displaying and controlling an image for displaying a first image having a first aspect ratio as a second image having a second aspect ratio, the method comprising: Storing pixel data of the first image in units of horizontal lines; Converting the number of lines including one display image of the first image to process the pixel data of the at least two lines stored in the storing step to display the first image at the second aspect ratio; And controlling the storage operation timing of the storing step so that the first image is not broken in the converting process of the converting step. 8. The image display and control method according to claim 7, wherein the controlling step includes controlling the timing of the storage operation in units of horizontal lines such that the line form of pixel data read from the memory means is a line format of an interlaced scanning system. . The method of claim 8, The first image comprises 480 lines of an interlaced scanning system, The second image comprises 480 lines of an interlaced scanning system, Pixel data for two lines is stored in the storing step, 480 lines are converted into 432 lines by processing the pixel data for the two lines of the conversion step, And the start timing of the first image is controlled to be 14 lines earlier than the start timing of the second image of the control step. 8. The image display and control method according to claim 7, further comprising: synthesizing pixel data of the first image and pixel data of the second image having the number of lines converted in the converting step. 8. The method of claim 7, further comprising: synthesizing the pixel data of the second image and the pixel data of the first image having the number of lines converted in the converting step, wherein the pixel data of the first image is synthesized. And read out in units of horizontal lines in the storing step to include the line form of the interlaced scanning system. 12. The method of claim 11, wherein the first image is a computer graphics image that includes square shaped pixels, and the second image is an MPEG format image that includes rectangular shaped pixels.

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