KR960015588B1 - Method and apparatus for delaying access of requester in parallel processing or multiple processing system - Google Patents

Abstract

applying the use of a bus and entering into competition for the use of the bus(S1-S3); investigating which responder generates an address in case of WIN in the bus competition(S4,S5); applying the use of a bus if a proposer exists, and investigating the state of the corresponding responder if there is no proposer; investigating whether an error exists in an information after investigating the state of the information showing the possibility of responding from the responder(S10-S12); ending after writing data in the corresponding address of the responder if the information is a write operation(S15,S16); applying the use of a bus after reading the information of the corresponding address if the information is a read operation(S17,S18); entering into the competition for the use of a bus(S19,S20); and ending after driving the read information in case of WIN in the bus competition(S21,S22).

Description

Method for delaying requestor access in computer system of parallel / multiprocess structure

1 is a block diagram schematically showing the configuration of a system to which the present invention is applied.

2 is a block diagram showing the configuration of a bus detector according to the present invention.

3 is a functional block diagram showing a relationship between a bus detector and its peripheral devices according to the present invention;

Figure 4 is a flow chart showing the function of the bus detector in accordance with the present invention.

The present invention relates to a method and apparatus for performing or delaying an access operation of a requestor to a responder according to a responder state in a parallel processing system or a multiprocessing system.

As shown in FIG. 1, in a computer system having at least two or more requesters sharing any one (or more) responders (e.g., storage), the basic processing between the requestor and the responder Frequently, the responder cannot respond to the request of the requester because of problems caused by the speed difference and the problem that two or more requestors want to access a single responder at the same time.

In the response operation cycle of the responder, which consists of information reading, reception response, memory access cycle, or information reading, reception response, memory access, bus request, and data drive cycle, memory access (when writing response) or memory access, bus request If there is another request from the requester to the responder that is in the data drive (on a read response) operation cycle (i.e., performing a read or write response operation), the responder signals an in-operation signal indicating that it is equalizing. It informs the requester to retry the request by providing the signal to the requester making the access fairy.

The requestor thus decrypts the signal provided from the responder and retries the same request as described (eg, starting from the bus usage request if the responder is a storage device).

As a result of the repetition of the same operation, the burden on the bus is increased, the processing speed of the requester is slowed, and the loss of the responder also needs to be accepted two or more times. Therefore, the performance of the system is reduced. Of defects are brought about.

In order to solve the problems described above, by reducing the access upper layer to the responder by a well-known response address distribution method, the number of retries of the requester is reduced, and as a result, the burden on the bus is reduced. Indirect methods have been used.

However, this method basically solves the problem of increasing the number of retries of the requestor due to the inability of the responder in the case of a large number of requestors (in a system as shown in FIG. 1 including a plurality of requestors). There is a limit.

The main object of the present invention is to reduce the bus burden of parallel processing or multiprocessing computer systems and to improve the performance of the system. In the above parallel or multiprocessing computer systems, the responder responds to the requestor's request. In order to reduce the system performance loss caused by retrying the same request due to the inability, the bus detector is placed in the requester and the response status is placed in the responder so that the requestor can recognize the response status of the responder whenever the bus is used. Therefore, the purpose of preventing the use of the bus in advance is to prevent the use of the bus in advance in case of accessing the responder in an unresponsive state by identifying whether the responder can be answered from the bus request preparation step.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the configuration of a bus detector that postpones an access request of a requestor when it is determined that the responder is in an unresponsive state immediately by identifying the responder's response state to the requestor's access request according to the present invention. It is also.

Referring to FIG. 2, the apparatus of the present invention decodes an address provided through the system bus 1 from any one requestor (see FIG. 1) so that the requestor requests access to a certain responder. Responder discriminator (2) for determining whether the answering machine has requested access by the requestor, and the response state of the responder, i.e., the waiting state for which the answering machine can immediately respond to the requestor; Access response status that delivers analysis results such as information decode status, abnormality of access request, and acknowledgment of the request, memory access status that fulfills the required meaning in the requested location To the request state of the bus that applied for the use of the bus, to deliver the result of the access to the requestor, etc. A response state detector (3) for detecting which state of the responder operation cycle is performed, a response state store (4) for holding and changing the response of the responder, and the operation cycle specification of the system bus (1) And a bus detector state sequential controller 5 for controlling the operation of the responder discriminator 2, the response state detector 3, and the response state store 4. As shown in FIG.

The sequential controller 5 is configured of a bus detector while the requestor and the responder transfer the request address or request address and data to the bus in accordance with the operation cycle specification of the system bus 1 and transfer the request address or the request address and data from the requestor to the responder or the requestor. Responder discriminator, response status detector, response status saver, etc. must be processed in order by connecting each detailed operation with the detailed operation of other components, so that correct results can be obtained. It plays the role of generating the start signal by setting the order of detailed operation of each component.

As described above, FIG. 2 is a block diagram showing the apparatus of the present invention together with the response state of FIG. 3, a bus sense state sequential controller 5, a responder discriminator 2, a response state detector 3, and a response state store. It is a bus detector composed of the group 4 and the like.

The response determiner 2 decodes the expected expected address to determine which responder should respond. The response state detector 3 responds to the responder, such as a standby state, information readout, acknowledgment response, memory access, or bus request. Detect which state is in the operation cycle.

The response state store 4 holds and changes the response state of each responder, and the bus detection state sequential controller 5 includes the responder discriminator 2, the response state detector 3, the response state store 4, and the like. It controls the operation of according to the system bus operation cycle specification.

FIG. 3 shows the functional blocks of the requestor and the responder, respectively, in the apparatus of the present invention, that is, the system to which the bus detector and the response state are applied (see FIG. 1).

The requester generates an address generation block 10 that generates an address to be made up of a CPU, a local memory, and various controllers, and temporarily stores an address or data, or a point in time at which an address or data is driven to or from a bus. A controlling data and address controller 20, a bus contender 30 that recognizes the application of bus usage and its consequences, and a bus detector 40 as in the description of FIG. 2 above.

The responder also has a storage device 50, which is an information storage place, a controller 60 that controls access to the storage device of the requester, and temporarily stores an address or data, or drives an address or data from / by bus. A data and address controller 20a for controlling the time point, and a response state machine 70 representing a memory access operation state, a data drive operation state, a memory lock operation state, a response wait state, and the like.

As described above with reference to FIG. 1, requestor 1 attempts to access responder A, while requestor 2 attempts to access responder A when responder A is running, causing responder A to drive a non-response signal to the bus. Requester 2 then recognizes this unresponsive signal and retries the access.

4 is a flowchart illustrating a control process from the requester requesting access to the responder to the responder responding to the request. The bus sensor according to the present invention recognizes and processes the state of the responder. .

First, when the access address is generated by the requestor (S1), the application for the use of the bus (S2), and the competition for the use of the bus (S3).

Subsequently, it is determined whether or not there is a win (WIN) in the competition of the buses (S4).

At this time, if it is determined that the bus has been lost (if no in S4), then the application for bus use is again performed (axis, return to S2), and if it is determined that the bus has been won (if yes in S4), the generated address is Check whether it is a transponder (S5).

Thereafter, the response state of the corresponding responder (that is, whether or not the response is possible) is examined (S6).

At this time, if it is determined that it is unresponsive (No at S6), the bus competition application active signal and the position of the bus competition are decoded and the bus applicant is examined (S7) to determine whether there is no applicant. (S8).

At this time, if it is determined that there is an applicant (YES in S8), the bus application is made again (that is, returning to S2), and if there is no applicant (NO in S8), the state of the responder is checked again (that is, Return to S5).

On the other hand, in step S6 above, if it is determined that the answering machine is in the response waiting state which is the answerable state of the responder state (YES), the bus is driven (S9).

Information indicating whether or not the answering machine is collected is collected from the responder (S10 and S11), and whether or not there is an error in the information (S12).

At this time, if it is determined that there is an error (YES in S12), the retry signal is driven (S13). If it is determined that there is no error (NO in S12), it is checked whether one of the read and write operations is performed (S14).

Subsequently, it is checked whether or not it is a write operation (S15), and if it is determined to be write (YES in S14), data is written to the corresponding address of the responder and terminated (S16).

In step S15, if it is determined that the read operation is performed (i.e., no), the information of the address is read and the use of the bus is applied (Sl7, Sl8)

Then, the read information is temporarily stored (S19), and the vehicle enters into competition again (S20).

If it is determined (S21) that it has been determined to win the bus competition (ie no), then reapply the use of the bus (return to S18), and if it is determined to win (if YES in S21), read the information to the bus. Drive and end (S22).

As described above, in the present invention, the requestor has its own bus detector and always recognizes the state of the responder, thereby identifying whether or not it is possible to respond from the bus request preparation step to access the responder in an unresponsive state. In this case, it is possible to prevent the bus from using this request, and as a result, it is possible to solve the problem of retrying the same operation of the requestor due to unnecessary bus usage and the transponder operation.

That is, according to the present invention, it is possible to reduce the bus burden and reduce the number of retries of the requestor by using the bus as an information exchange path and increasing the response device access success rate in a parallel processing or multiprocessing computer system having a shared response device. .

Claims (2)

A method of performing or delaying an access operation of a requestor in accordance with a responsive state of the responder in a parallel processing system or a multiprocessing system having at least one requestor and a responder; When the access address is generated by the requestor, applying for the use of the bus and entering a competition for the use of the bus (S1 to S3); Determining whether the player has won the bus competition, and if the player is found to have lost the bus competition, resubmits the use of the bus, and if it is found that he has won the bus competition, examining which responder is the generated address ( S4, S5); Investigating the response status of the responder and determining that there is no response status, examining bus applicants, and determining whether there are no applicants (S6 to S8); If it is determined that there is an applicant, performing the bus use application again; if it is determined that there is no applicant, again examining the state of the responder; In the corresponding responder response state investigation step (S6), if the responder is found to be in a response state, the bus is driven, the information indicating whether or not the answering machine is collected, the state of the information is examined and the error is found in the information. Checking whether there is any (S10-S12); If it is determined that there is an error, driving a retry signal, and if it is determined that there is no error, checking whether one of the read and write operations is performed (S13, S14); Checking whether it is a write operation and writing data to the corresponding address of the answering machine if it is determined to be written (S15, S16); In the above step, if it is determined that the read operation (S17, S18) to read the information of the address and to use the bus; Temporarily storing the read information and entering into a race to use the bus again (S19 and S20); Re-applying the use of the bus if it is determined to have won the bus competition, and if it is determined to be successful, driving and terminating the read information to the bus (S21, S22). A method for deferring requestor access to rescue computer systems. In a parallel processing system or a multiprocessing system having at least one requestor and a responder connected to the system bus 1, the access operation of the requestor is performed according to the response state of the requester. In a device for acting or acting; The device comprises a responder discriminator (2) which deciphers an address provided through the system bus (1) from any one requester and determines which responder the accessor requests access to, and the response state of the responder is A response state detector (3) for detecting which state of the transponder operation cycle is present, a response state store (4) for holding and changing the response of the corresponding responder, and the operation cycle standard of the system bus (1); Computer system comprising a responder discriminator (2) and a bus detector state sequential controller (5) controlling the operation of the response state detector (3) and the response state store (4) Requestor access deferred device.