KR960012355B1 - Controller for supporting cache-to-cache data transfer in multiprocessor system - Google Patents

Abstract

a cache - to - cache controller(10) controlling the cache - to - cache transfer by generating control signals; a transfer type controller(30) making/inspecting the data transfer type; a bus receiver/driver(50) storing and receiving the signal driven in a pended protocol bus(P-bus); an address/data buffer and parity checker(20) storing the address and data driven in a processor and in a cache memory and checking the parity of the address and the data; and an ID comparator(40) comparing DI with SI driven in the pended protocol bus.

Description

Cache-to-Cache Direct Data Transfer Control in Multiprocessor System

1 is a schematic diagram of a system having multiple processors.

2 is a sequence of receiving data of direct transmission between caches.

3 is a sequence of sending data of direct transfers between caches.

4 is a detailed block diagram of the present invention.

5 is a state flowchart of a control circuit of the present invention.

* Explanation of symbols for main parts of the drawings

P-Bus: Pended Protocol Bus

C2CM: Cache-to-Cache Transfer Module

C2C: Cache-to-Cache Data Transfer

10: inter-cache controller 20: buffer and parity checker

30: transmission type controller 40: ID comparator

50: bus receive and driver

The present invention relates to an apparatus supporting direct data transfer between a cache memory and a cache memory in a system in which a plurality of processor modules and a plurality of memory modules are connected through a Pended Protocol Bus.

In multiprocessor systems with cache memory, the main memory is shared, so it is often necessary to move data from one cache memory to another.

Previously, in this case, the cache data was once moved to the dynamic random access memory (DRAM) in main memory, and then another cache read the data.

This method requires two data transfers through the system bus and one write and read operation of the DRAM, which is three to five times slower than the cache memory.

The pending protocol bus is the bus used in systems with multiprocessor environments.

This is a bus that accesses memory by dividing a data transfer into request and response steps.

In this protocol, one processor does not occupy the bus for the time to access memory for data transfer, so long memory access times do not affect the transfer speed of the bus.

In addition, multiple processors can send overlapping memory access requests, and memory responses are also overlapped.

Thus, it is an absolutely advantageous protocol for buses in multiprocessor environments.

A multiprocessor system is proposed as a method for performing more tasks per unit time than a single processor by simultaneously executing multiple processors. Multiprocessor systems virtualize the use of a single shared memory, which means that multiple processors can share and use any data in shared memory at the same time.

Therefore, the memory that can move at the same speed as the processor and provide data is the most ideal, but the access speed of the memory is less than that of the processor.

In addition, the complexity of dealing with large amounts of data is increasingly demanding more memory as well as computer performance. In terms of cost, DRAM is known to be the most advantageous to date for the construction of large amounts of memory.

However, because DRAMs are not as fast as the processor, the processor places cache memory with faster operating speeds than DRAM to handle faster tasks.

In short, a cache is a storage device that stores data and instructions needed by the processor.

Caches are also often used to compensate for I / O (input and output) devices, which are slower than DRAM. Wherever the cache is, the principle is the same.

Most programs and data processing are based on the principle of data repeatability, where the same information or code is needed again and again, and data locality, where information near the address of a used data is likely to be reused soon.

Cache implementations on uniprocessor systems are relatively easy, but multiprocessor caches are quite complex. There may be a variety of problems, but they can be summarized in roughly three ways:

First, the demand for a shared memory cache from multiple processors causes a memory conflict.

In other words, if multiple processors require data of the same address, arbitration is required.

Second, a cache can sometimes have copies of data in multiple caches, and this is a problem of keeping the copy data consistent.

This remains the most difficult problem in multiprocessor systems using caches. Third, there is a bandwidth problem in a multiprocessor system using a common bus. The larger the multiprocessor system, the longer the time to perform data communication.

SUMMARY OF THE INVENTION The present invention has been proposed to improve these problems in multiprocessor systems using shared cache memory. [0005] Cache-to-cache data transfer (hereinafter referred to as "C2C") can be used in DRAMs. The goal is to improve the overall system performance by presenting a way to use only one bus without reading or writing once.

By using the direct data transfer method from cache to cache, the data inconsistency problem caused by distributing memory data copies in multiple processor-only caches can be simplified and solved easily. Reduces bus bottlenecks caused by frequent use of common buses by writing.

It also helps reduce data errors that can occur during dual transfers of data from cache to memory and from memory to cache.

1 shows the overall configuration of a system to which the present invention is applied.

In this system, n + 1 processor modules (P0 to Pn) and memory modules are connected to a pending protocol bus (hereinafter referred to as 'P-Bus').

The position to which the present invention is applied is the inside of each processor module, and the gist of the present invention is a Cache-to-Cache Transfer Module (hereinafter referred to as 'C2CM') shown in bold in FIG. Corresponds to Cache data of the processor module P0 may be transmitted to the cache of the processor module P1 or cache data of the P1 may be transmitted to the P0.

FIG. 2 shows a sequence of time-dependent steps of a module receiving data when performing direct data transfer between caches on a P-Bus.

3 shows a sequence of time-sequences of the module sending data when performing direct data transfer between caches on the P-Bus.

When transferring cache data, one processor module starts a read transfer, and the other processor module whose data you want to read starts a write transfer.

FIG. 2 shows a typical read process on the P-Bus. At t0, the processor module P0 drives an address ADDR, a transfer type (TT) and its own location (SI) to be read. There are two types of transmission (TT): CRD and EXR.

CRD is a form of transmission that occurs when a processor requests data at that address to read data.

EXR is a form of transfer that occurs when a processor reads to write some value to the data at that address. In the case of CRD, the cache state may be V (Vaild) or S (Shared). In the case of EXR, the cache state is D (Dirty).

In the case of these two types of transfers, other caches can perform direct data transfer (C2C) between caches.

At t1, each of all the other processor modules checks whether processor module P0 has the desired data. At this time, the address ADDR and the transmission type TT are determined. This investigation period should not be longer than one clock period of the P-Bus.

At t2, the processor module holding the desired data drives an ITV signal on the P-Bus indicating that it has that data and will send it through the P-Bus.

At this time, the driven AACK indicates that the ADDR and the TI driven at t0 are normally recognized.

If the processor module P0 confirms that nobody drives the ITV signal at t2, then the direct data transfer (C2C) between caches does not occur and the memory knows to send the data. On the other hand, when the ITV signal is driven, the other processor module knows to send the data it wants and waits for the data to arrive.

At t_0, when data is driven, processor module P0 compares DI (Destination Identification) with its SI (Source Identification). If the result is the same, it knows its data and P0 reads it.

At t_1, it is determined whether the read data has an error. It checks with data parity.

At t_2, if the parity is checked and there is no error, the CDK signal is driven to indicate that data has been received normally. If the CDK is not running, the processor module P0 retries the direct data read transfer between caches.

4 shows the configuration of an inter-cache transmission module (C2CM) according to the present invention. The inter-cache transmission module (C2CM) is composed of five sub modules as follows.

Referring to FIG. 4, the Inter-Cache Transmission Module (C2CM) includes a Cache-to-Cache Controll (C2C-CNTR) 10 and an Address / Data Buffer and Parity Checker; PC (20), Transfer Type Controller (TT-CNTR) 30, Identity Comparator (ID-CMP) 40, and Bus Receiver / Driver (B) -RD) 50. The function of each submodule is as follows.

The inter-cache controller (C2C-CNTR) 10 is a central portion of the inter-cache transmission module (C2CM), and generates a signal for controlling each submodule. When a data read or write is requested by the processor, the inter-cache controller 10 generates a signal for controlling the bus receiving and driver (B-RD) 50 to drive the ADD, TT, and SI signals through the P-Bus. do.

In addition, a signal for holding data and an address driven by a processor or P-Bus in the buffer and parity checker (ADB-PC) 20 is driven. In order to capture data driven in the P-Bus, the result of the ID comparator (ID-CMP) 40 is used.

The inter-cache controller 10 has a state machine for generating a control signal for this, which will be described in detail later with reference to FIG.

The buffer and parity checker (ADB-PC) 20 is composed of a buffer that holds an address and data driven by a processor or a P-Bus. It also includes a parity checker that determines whether the address and data are normal.

The transmission type controller (TT-CNTR) 30 generates a transmission type for P-Bus transmission according to the type of cycle driven by the processor, and also sees the transmission type driven in the P-Bus and participates in the transmission. Decide if you should.

The ID comparator (ID-CMP) 40 compares its SI and DI driven in the P-Bus. This comparator 40 allows the data transmitted by the other processor to know if it is desired by the inter-cache transfer module (C2CM) itself.

The comparator 40 also has a function of storing the SI driven in the read transfer in its register. This function is necessary to send this SI to DI when sending the data of own (C2CM) to the other party later.

The bus receiver and driver (B-RD) 50 is composed of elements for catching a signal driven in the P-Bus or driving a signal in the P-Bus. The inter-cache controller 10 generates a control signal for sending a signal to the bus or catching a signal to the bus. Types of signals driven or received by the bus receiver and driver 50 include TT, DI, SI, CDK, A, and D as shown in FIG.

5 shows a state flow diagram of the inter-cache controller 10. In FIG. 5, # represents a logical OR, and represents a logical AND. The intercache controller 10 generates signals for controlling all parts B-RD and DB-PC of the intercache transmission module C2CM according to this state flowchart. The operation of the state flow diagram is as follows.

The base clock of this state flow chart uses the reference clock BCLK of the P-Bus.

• IDLE: When the Data Transfer Request (PRQ) is received from the processor, the state transitions to DALATCH. If there is no request for transmission, it stays in its own state.

DALATCH: A step in which the processor gets a signal from the processor or cache memory to perform a read or write operation. In case of reading, PCRD and PEXR are driven, and in case of writing, PITW is driven. If it is read, it drives CC-PAL. If it is a write, it drives CC-PAL. In the case of a write, the processor performs a transfer that sends out its own data because another processor has requested data from its cache. The state transitions directly to ADDDR.

• ADDR: The address is driven on the P-Bus. In case of CRD or EXR transmission, TT and SI are also driven. In case of ITW transmission, TT is driven together. If PITW is running, it will transition to DDRV, otherwise to AKWAIT.

• In case of 1TW transmission, data is transferred to BCLK immediately after driving address. In this case, DI is also driven to tell where the driving data should be sent.

AKWAIT: Waits for 1BCLK because it takes time for another processor module to determine if it has been successfully sent after driving the address.

ADDCHK: This is a state for judging the result of address transmission. If the result is judged to be an error, it is transitioned back to ADDR state, otherwise it is transitioned to DWAIT if CRD or EXR, and to CDKWAIT if ITW.

CDKCHK: Determine the result of data transfer. If the CDK is running, complete the ITW transfer normally and start the CDONE. Otherwise it transitions to ADDRV state to retry the ITW transmission.

• DWAIT: Waiting for the requested data to be sent. At this time, the B-RD continuously latches data and DI driven on the P-Bus every BCLK. The B-RD compares the B-DI by providing it to the ID-CMP. The C2C-CNTR drives the CC-BDL and transitions to the DCHK state because its data has arrived when the ID-CMP MYID is driven.

ㆍ DCHK: Checks the status of the data with the status of checking the transmitted data and the data parity driven with the data. If the result of the data inspection examined by ADB-PC is abnormal, the state is changed to ADDDR and retry. Otherwise, when DPOK is driven, the state transitions to CDKDR.

• CDKDR: The CDK is driven because there is no error in the transmitted data. Run the CDK to inform the sending party that the receiving party has successfully taken the data. Complete the read transfer and run CDONE.

Claims (1)

A multiprocessor system in which at least two processors are coupled on a pending protocol bus, comprising: inter-cache transfer modules (C2CMs) coupled to each of the processors to perform direct cache transfers between caches; Each module includes an inter-cache controller 10 for generating predetermined control signals for direct data transfer between caches to control inter-cache transfers, a transfer mode controller 30 for creating or checking a data transfer form, and the Fendi A bus receiver and driver 50 for storing or driving a signal driven on a protocol protocol bus, and an address and data driven by a processor and cache memory, or a bus receiver and driver 50 driven on the pending protocol bus through the bus receiver and driver 50. Buffer and parity checker for storing data or checking parity of data and addresses (2 0) and an ID comparator 40 which compares DI and SI driven on the pending protocol bus and sends the result to the inter-cache controller 10. Data transfer support control device.