KR100368744B1 - Retry apparatus and method for maintaining cache consistency in hi-fi bus - Google Patents

Abstract

PURPOSE: A retry apparatus and method for maintaining a cache consistency in a hi-fi bus is provided to prevent a deadlock phenomenon of a system by simply checking a cache consistency maintaining operation at a pertinent address region to re-try an algorithm. CONSTITUTION: An RQ(Requester) module requests to a bus use, an arbitration is made. When the RQ module obtains a bus privilege, it drives an address of a region desired to be accessed on the bus. In case of reading, the RQ module waits for an acknowledge(ACK) signal from an RP(Responder) module. If a response to a received ACK signal is a cache signal or an LBUSY signal, the RQ module comes to a standby/sampling address acknowledge(ACK) unit and checks whether a cache-related operation at the corresponding address region has been completed. Upon checking, if the cache signal or the LBUSY signal has been released, the RQ module is transited to a request and acquisition state to request a bus use and acquire a bus privilege, and repeatedly performs a bus cycle. In case of writing, the RQ module drives an address and a data, and then waits for an ACK response. If a response result to a received ACK signal is a cache signal or an LBUSY signal, the RQ module performs a re-trying operation through the standby/sampling address ACK unit as in the case of reading.

Description

Retry apparatus and method for maintaining cache identity on Hi-Pi bus

TECHNICAL FIELD The present invention relates to a Hi-Pi bus. In particular, the present invention relates to a high-speed system for improving the high speed and stability of a system by preventing a presentation delay and a bottleneck caused by a RETRY algorithm. A retry apparatus and method for maintaining cache identity on a Hi-Pi bus.

Conventionally, a retrying method for maintaining cache identity on a Hi-Pi bus is performed by a requester (RQ) module wishing to use a system bus as shown in FIG. Bus arbitration will then take place.

Then, the RQ module obtained the bus right during the arbitration process drives the corresponding address on the address bus according to the bus protocol.

Here, in the case of READ, it waits for an acknowledgment (ACK) signal indicating that an address has been received from a responder (RP) module.

Thereafter, if there is no error in the response of the transmitted ACK signal, the RQ module waits for data to be transmitted from the corresponding address, stores the transmitted data, and ends the bus cycle.

However, if the acknowledgment (ACK) response result is a cache signal or LBUSY signal, the RQ module drives the transmission completion (DONE) or transmission failure (FAIL) signal simultaneously because the cache related operation is not performed in the corresponding area. Have the user retry the area.

Here, the CACHE signal means a DIRTY signal or a SNACK signal. The DIRTY signal is a signal for maintaining cache identity and indicates that data to be transmitted is modified in the cache and is not the same as the memory.

The SNACK signal is also a signal for maintaining cache identity, indicating that an error has occurred during the cache identity maintenance operation.

The LBUSY signal also indicates that the requested area is locked.

On the other hand, in the case of write, the RQ module drives data after address driving and waits for an acknowledgment (ACK) response signal to be transmitted in the corresponding address area.

Thereafter, if there is no abnormal result of the transmitted acknowledgment (ACK) response signal, the RQ module waits for a response to the data transmission and ends the bus cycle.

If the response result of the transmitted ACK response signal is a cache signal or an LBUSY signal, the RQ module retries as in the case of READ.

However, this method of maintaining cache identity on a Hi-Pi bus continues to retry until the RQ module releases the signal when a retry is performed by a CACHE or LBUSY signal. At this time, if the priority of the RQ module requesting the bus use is higher than the corresponding RQ module or the bus request is made first, the signals are not easily released.

Therefore, the number of retries of the RQ module that intends to use the bus increases, and in severe cases, this may cause the entire system to become a bottleneck (DEADLOCK).

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a presentation by simply checking the cache identity maintaining operation in a corresponding address region without requesting continuous bus use when performing a retry algorithm. By doing so, it is not influenced by priority or request order among RQ modules, and it is possible to prevent bottleneck of the system due to maintaining cache identity, and to secure the speed and safety of the system.

Technical means for achieving the object of the present invention is

Local bus address storage means for storing an address driven through a local bus in response to a bus use request;

System bus address storage means for storing an address fetched from the system bus,

Address comparison means for comparing a local address stored in the local bus address storage means with an address fetched in the system bus address storage means and outputting a signal as a result;

And a waiting / sampling address recognizing means including recognizing signal storage means for storing the recognition signal in accordance with the result of the comparison signal output from the address comparing means.

In addition, a method for achieving the object of the present invention is

When the RQ module requesting to use the system bus makes a request to use the bus, arbitration is performed, and the first process of driving the address of the area to which the RQ module, which has obtained the arbitration of the bus, wants to access on the bus,

In the case of READ in the first process, a recognition signal transmitted from the RP module is searched. If there is no error in the recognition result, the controller waits for data to be transmitted from the corresponding address, and stores the data and ends the bus cycle. 2 courses,

In the case of WRITE in the first process, data is driven after address driving, and a recognition response signal driven to the corresponding address area is searched. If there is no error in the recognition response result, the bus cycle is terminated after waiting for a response to the data. With the third process,

If the response result of the recognition signal in the second process and the third process is a cache signal or a LBUSY signal, it transitions to the standby / sampling state to check whether the cache related operation in the corresponding address area is completed and the check result is still If it is a CACHE signal or LBUSY signal, it transitions back to the standby / sampling state and repeats the same process.If the check result shows that the CACHE or LBUSY state is released, it transitions to the bus use request and bus license acquisition state and then cycles the bus. It consists of a fourth process of repeating.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

2 is a block diagram illustrating a standby / sampling address recognition (ACK) unit according to the present invention, and includes a local bus address storage unit 102a for storing an address driven through the local bus 101 in response to a bus use request. And a system bus address storage 102b for storing an address fetched from the system bus 103, and a local address stored in the local bus address storage 102a and a system bus address storage 102b. an address comparison unit 102c for comparing the fetched addresses and outputting a result signal, and a recognition signal storage unit 102d for storing the recognition signal in accordance with the result of the comparison signal output from the address comparison unit 102c. It consists of a standby / sampling address recognition (ACK) unit 102, including.

The operation and effect of the present invention configured as described above will be described with reference to FIGS. 2 and 3.

First, when the RQ module which wants to use the system bus makes a request for bus use, arbitration is performed.

After that, the RQ module having obtained the arbitration bus usage rights drives the address of the area to be accessed on the bus.

Here, in the case of READ, it waits for an acknowledgment (ACK) signal to be transmitted from the RP module.

If there is no error in the response of the transmitted ACK signal, the RQ module waits for data to be transmitted from the corresponding address, stores the data, and ends the bus cycle.

However, if the response of the transmitted acknowledgment (ACK) signal is a cache signal or a LBUSY signal, the RQ module goes to the standby / sampling address recognition (ACK) unit 102 and checks whether the cache related operation in the corresponding address area is completed. Will be checked.

That is, the standby / sampling address recognition (ACK) unit 102 operates as follows.

First, the waiting / sampling address recognition (ACK) unit 102 stores an address driven by the host on the local bus 101 in the internal bus address storage unit 102a.

In addition, the standby / sampling address recognition (ACK) unit 102 stores the address that is driven and then fetches the address appearing on the system bus 103 to the system bus address storage unit 102b.

Then, the address comparison unit 102c in the waiting / sampling address recognition (ACK) unit 102 compares the stored local address with the fetched system bus address, and compares this signal with the same address as a result of the comparison. An acknowledgment (ACK) signal storage unit 102d is transmitted.

Accordingly, the acknowledgment (ACK) storage unit 102d inside the standby / sampling address recognition (ACK) unit 102 has a cache signal that is fetched according to the transmitted signal. Or check whether LBUSY signal is present.

After that, if the check result is still in the cache signal or the LBUSY signal state, the RQ module goes back to the standby / sampling address recognition (ACK) unit 102 and repeats the same process.

However, if the check result indicates that the CACHE or LBUSY signal is released, the RQ module transitions to the REQUEST & ACQUISITION state and repeats the bus cycle.

In addition, in the case of write (WRITE), the RQ module drives data after the address driving and waits for an acknowledgment (ACK) response in the corresponding address area.

Thereafter, if there is no error in the response of the transmitted ACK signal, the RQ module waits for a response to the data to be transmitted, stores the transmitted data, and ends the bus cycle.

If the response of the transmitted acknowledgment (ACK) signal is a cache signal or a LBUSY signal state, the RQ module restarts through the standby / sampling address recognition (ACK) unit 102 as in the case of the READ. Perform the RETRY process.

As described above, the present invention does not affect the priority or request order between RQ modules by performing retry only by checking the cache equality maintaining operation in the corresponding address region without continuously requesting the use of the bus when performing the retry algorithm. In addition, it is possible to prevent the bottleneck of the system due to the problem of maintaining cache identity, as well as to secure the high speed and safety of the system.

1 is a retry flow diagram for maintaining cache identity on a conventional Hi-Pi bus.

2 is a block diagram of a standby / sampling address recognition (ACK) unit according to the present invention.

3 is a retry flow chart for maintaining cache identity on a Hi-Pi bus in accordance with the present invention.

*** Explanation of symbols for the main parts of the drawing ***

101: LOCAL BUS 103: system bus

102: standby / sampling address recognition (ACK) unit

102a: LOCAL BUS ADDRESS storage

102b: SYSTEM BUS ADDRESS storage

102c: address comparison unit 102d: acknowledgment (ACK) signal storage unit

Claims (2)

Local bus address storage means for storing an address driven through the local bus 101 according to a bus use request; System bus address storage means for storing an address fetched from the system bus 103; Address comparison means for comparing a local address stored in the local bus address storage means with an address fetched in a system bus address storage means and outputting a signal as a result; Hi-Pi bus comprising standby / sampling address recognition (ACK) means configured to include recognition signal storage means for storing recognition signals in accordance with the comparison signal output from the address comparison means Retry device to maintain cache identity in the. When the RQ module requesting to use the system bus makes a request to use the bus, arbitration is performed, and the first process of driving the address of the area to which the RQ module, which has obtained the arbitration of the bus, wants to access on the bus, In the case of READ in the first process, the latch address recognition signal transmitted from the RP module is searched. If there is no error in the recognition result, it waits for data to be transmitted from the corresponding address, and stores the data and ends the bus cycle. With the second process, In the case of WRITE in the first process, data is driven after address driving, and a recognition response signal driven from the corresponding address area is searched. If there is no error in the recognition response result, the bus cycle is terminated after waiting for a response to the data. With the third process, If the response result of the recognition signal in the second process and the third process is a cache signal or a LBUSY signal, it transitions to the standby / sampling state to check whether the cache related operation in the corresponding address area is completed and the check result is still If it is a CACHE or LBUSY signal, the process returns to the standby / sampling state and repeats the same process. If the check result shows that the CACHE or LBUSY state is cleared, it transitions to the bus request and license acquisition state and repeats the bus cycle. A retry method for maintaining cache identity on a Hi-Pi bus, comprising the fourth step.