KR970072812A - Retry device and method for maintaining cache identity on a Hi-Pi bus - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides cache equalization maintenance on a Hi-Pi bus to improve system security and safety by preventing retry delays and DEADLOCKs that can occur in a retry algorithm. And more particularly, to a retry apparatus and method.

To this end, the present invention relates to a local bus address storage means for storing an address driven via a local bus in response to a bus use request, a system bus address storage means for storing an address fetched from the system bus, Address comparison means for comparing the local address and the fetched address with the system bus address storage means and outputting the resultant signal; and recognition signal storage means for storing the recognition signal in accordance with the comparison signal output from the address comparison means The RQ module, which is provided as the standby / sampling address recognizing means, arbitrates for the bus use request when the RQ module to use the system bus makes a request to use the bus. As a result of the arbitration, The first In the case of reading in the first step, the RP module searches for a recognition signal to be transmitted. If the recognition result is not abnormal, it waits for data to be transferred from the address, stores the data when the data is transferred, And a second step of driving the data after the address driving and retrieving the recognition response signal driven from the address area and waiting for a response to the data if the recognition result is not abnormal, If the response signal of the recognition signal is a cache signal or an LBUSY signal in step 3, step 2, and step 3, a transition is made to the standby / sampling state to check whether the cache- If it is still a cache signal or an LBUSY signal, it transitions to the standby / sampling state again When repeating the same procedure, and the check result cache or LBUSY state is released to shift to a bus use request and the license acquisition status comprises a fourth step of repeating a bus cycle.

Description

Retry device and method for maintaining cache identity on a Hi-Pi bus

Since this is a trivial issue, I did not include the contents of the text.

FIG. 2 is a block diagram of a standby / sampling address acknowledgment (ACK) unit according to the present invention; FIG. 3 is a flow chart of a retry for maintaining cache identity in a Hi-Pi bus according to the present invention;

Claims (2)

Local bus address storage means for storing an address driven via the local bus 101 in response to a bus use request, system bus address storage means for storing an address fetched from the system bus 103, An address comparison means for comparing the local address stored in the storage means with an address fetched by the system bus address storage means and outputting a resultant signal; And a standby / sampling address acknowledgment (ACK) unit configured to include a recognition signal storage unit. The retry apparatus for maintaining cache identity in a Hi-Pi bus. A first step in which an arbitration is performed when an RQ module that wishes to use the system bus makes a bus use request and an RQ module obtained as a result of the arbitration results in driving an address of an area to be accessed on the bus; If it is read in step 1, the RP module searches for a latch address recognition signal to be transmitted. If the recognition result is not abnormal, it waits for the data to be transferred from the address, stores the data when the data is transferred, and terminates the bus cycle (WRITE) in the first step, the data is driven after the address driving and the recognition response signal driven from the address area is searched. If the recognition response result is not abnormal, a response to the data is waited A third step of terminating the bus cycle later, and a third step of terminating the bus cycle in the second and third steps If the response result of the recognition signal is a CACHE signal or an LBUSY signal, a transition is made to the standby / sampling state, and it is checked whether or not the cache related operation in the corresponding address area is completed. If the check result is still a CACHE signal or an LBUSY signal And repeats the same process by transiting to the standby / sampling state. When the cache state or the LBUSY state is released as a result of the check, a transition is made to a bus use request and a use right state to repeat the bus cycle. A retry method for maintaining cache identity on a Hi-Pi bus. ※ Note: It is disclosed by the contents of the first application.