KR960002006A - Cache Memory Filtering Device of Multiprocessor - Google Patents

Cache Memory Filtering Device of Multiprocessor Download PDF

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KR960002006A
KR960002006A KR1019940015666A KR19940015666A KR960002006A KR 960002006 A KR960002006 A KR 960002006A KR 1019940015666 A KR1019940015666 A KR 1019940015666A KR 19940015666 A KR19940015666 A KR 19940015666A KR 960002006 A KR960002006 A KR 960002006A
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South Korea
Prior art keywords
tag
memory
processor
information
invalidation information
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KR1019940015666A
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Korean (ko)
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KR960015583B1 (en
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임신일
최종찬
박병관
함종식
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김정덕
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array

Abstract

본 발명의 다중프로세서의 캐시메모리 필터링장치는 각 프로세서의 외부에서 태그를 관리하여 무효화정보가 발생되어 전송될 때마다 프로세서가 자신의 캐시를 검색하지 않도록 함으로써 각 프로세서의 처리효율을 향상 시킬 수 있다. 본 발명의 필터링장치는 다중프로세서 시스템에서 연속된 태그관리를 위하여 15단계의 FIFO메모리를 내장하고 있다. 그 구성은 다중프로세서시스템에서 상기 각 내부태시메모리의 태그내용과 동일한 내용의 태그를 저장하는 태그메모리, 상기 각 프로세서로부터 전송된 무효화정보를 받아 상기 태그메모리에 저장된 내용중에 그 무효화정보의 어드레스정보와 동일한 어드레스정보가 있는가를 비교판단하는 수단, 및 상기 비교 판단수단으로부터 출력신호를 받아, 동일한 어드레스정보가 상기 태그메모리에 있는 경우 상기 무효화정보신호를 상기 태그메모리가 종속된 프로세서에 공급하고, 동일한 어드레스정보가 없을 경우 상기 비교판단수단으로부터의 출력신호를 무시해버리는 태그관리수단을 포함한다.The cache memory filtering apparatus of the multiprocessor of the present invention can improve the processing efficiency of each processor by managing a tag outside each processor so that the processor does not search its cache whenever invalidation information is generated and transmitted. The filtering device of the present invention includes a 15-step FIFO memory for continuous tag management in a multiprocessor system. The configuration includes a tag memory for storing a tag having the same contents as the tag contents of each internal latency memory in a multiprocessor system, the address information of the invalidation information among the contents stored in the tag memory upon receiving invalidation information transmitted from each processor. Means for comparing whether or not there is the same address information, and receiving an output signal from the comparison determining means, when the same address information is in the tag memory, supplying the invalidation information signal to a processor to which the tag memory depends, and providing the same address information. Tag management means for ignoring the output signal from the comparison determination means if there is no error.

Description

다중프로세서의 캐시메모리 필터링장치Cache Memory Filtering Device of Multiprocessor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 다중프로세서의 캐시메모리 필터링장치가 채용된 시스템의 개략적인 블록도이다,2 is a schematic block diagram of a system employing a multiprocessor cache memory filtering apparatus according to the present invention.

제3도는 본 발명에 의한 다중프로세서의 캐시메모리 필터링장치의 보다 상세한 블록도이다,3 is a more detailed block diagram of a multiprocessor cache memory filtering apparatus according to the present invention.

제4도는 본 발명에 의한 캐시메모리 필터링을 처리하는 과정에 있어서 파이프라인 개념도를 도시한 개념도.4 is a conceptual diagram illustrating a pipeline conceptual diagram in a process of processing cache memory filtering according to the present invention.

Claims (8)

각 프로세서가 읽거나 쓰기동작을 할떼 데이타를 전송하여 저장하기 위하여, 상기 각 프로세서에 내장된 내부캐시메모리를 갖는 다중프로세서의 캐시메모리 필터링장치에 있어서, 상기 각 내부캐시메모리의 태그내용과 동일한 내용의 태그를 저장하는 태그메모리; 상기 각 프로세서로부터 전송된 무효화정보를 받아 상기 태그메모리에 저장된 내용중에 그 무효화정보의 어드레스정보와 동일한 어드레스정보가 있는 가를 비교판단하는 수단; 및 상기 비교판단수단으로부터의 출력신호를 받아, 동일한 어드레스정보가 상기 태그메모리에 있는 경우 상기 무효화정보를 상기 태그메모리가 종속된 프로세서에 공급되고, 동일한 어드레스정보가 없는 경우 상기 비교판단수단으로부터의 출력신호를 무시해버리는 태그관리수단을 포함하는 다중프로세서의 캐시메모리 필터링장치.In the multiprocessor cache memory filtering apparatus having an internal cache memory built in each processor, so as to transmit and store data as each processor reads or writes, the same contents as the tag contents of the respective internal cache memories. A tag memory for storing a tag; Means for receiving the invalidation information transmitted from each processor and comparing and determining whether there is the same address information in the contents stored in the tag memory as the address information of the invalidation information; And receiving the output signal from the comparison judging means and supplying the invalidation information to the processor to which the tag memory depends if the same address information is in the tag memory, and outputting from the comparison judging means if there is no same address information. Cache processor filtering apparatus of a multiprocessor comprising a tag management means for ignoring the signal. 제1항에 있어서, 각 프로세서로부터의 무효화정보를 태그메모리에 저장된 프로세서의 내장캐시메모리의 내용과 비교함이 없이 일단 저장한 후 순차적으로 비교하기 위한 FIFO메모리를 더 포함하는 것을 특징으로 하는 다중프로세서의 캐시메모리 필터링 장치.The multiprocessor of claim 1, further comprising a FIFO memory for sequentially comparing the invalidation information from each processor with the contents of the internal cache memory of the processor stored in the tag memory and sequentially comparing the invalidation information. Cache memory filtering device. 제1항에 있어서, 상기 태그관리수단은 상기비교기로부터의 적중신호를 받아 태그메모리에 무효화정보에 따른 데이터의 업데이팅을 수행하도록 하는 태그관리기를 포함하는 것을 특징으로 하는 다중프로세서의 캐시메모리 필터링 장치.The apparatus of claim 1, wherein the tag management unit comprises a tag manager configured to receive a hit signal from the comparator and to update data according to invalidation information to a tag memory. . 제1항에 있어서, 상기 태그관리수단은 상기 비교판단수단으로부터 적중신호가 발생한 경우 프로세서에 내장된 캐시메모리의 검색을 위한 신호를 출력하여 프로세서의 내부캐시메모리의 태그를 무효화시키고, 이와 동시에 동일한 동작을 복조된 태그메모리에도 지원하기 위하여 태그메모리의 내용을 무효화시키는 것을 특징으로 하는 다중프로세서의 캐시메모리 필터링 장치.2. The method of claim 1, wherein the tag management means outputs a signal for searching the cache memory built in the processor when a hit signal is generated from the comparison determination means to invalidate a tag of the internal cache memory of the processor and at the same time the same operation. And invalidating the contents of the tag memory to support the demodulated tag memory. 제2항에 있어서, 상기 FIFO메모리에 내용을 쓰거나 읽기 위한 우선순위를 제공하며, 버스에 중재신호를 만들어 프로세서에 일정한 프로토콜로 무효화정보를 전달하도록 여러가지 제어신호를 발생하는 상태제어수단을 더 포함하는 것을 특징으로 하는 다중프로세서의 캐시메모리 필터링 장치.3. The apparatus of claim 2, further comprising: status control means for providing a priority for writing or reading content in the FIFO memory, and for generating various control signals to create an arbitration signal on a bus and to pass invalidation information to a processor in a predetermined protocol. Cache memory filtering device of a multiprocessor, characterized in that. 제5항에 있어서, 상기 각 프로세서에 입력되는 무효화정보를 파이프라인화하여 제1파이프라인에서는 태그메모리의 내용과 상기 무효화정보를 비교하여 태그에 무효화쓰기를 수행하고 제2파이프라인에서는 FIFO메모리에 무효화정보를 저장하도록 함으로써 매 클럭마다 입력되는 무효화정보를 처리할 수 있는 다중프로세서의 캐시메모리 필터링 장치.6. The method of claim 5, wherein the invalidation information input to each processor is pipelined so that the first pipeline compares the contents of the tag memory with the invalidation information and writes the invalidation to the tag. The second pipeline writes the invalidation information to the FIFO memory. An apparatus for filtering cache memory of a multiprocessor capable of processing invalidation information input every clock by storing invalidation information. 제6항에 있어서, 상기 프로세서의 수는 3개로 하여 2개의 프로세서의 입력들을 필터링를 수행하지 않도록하고, 나머지 1개의 프로세서 입력을 필터링을 수행하도록 하는 다중프로세서의 캐시메모리 필터링장치.7. The cache memory filtering apparatus of claim 6, wherein the number of processors is three so as not to filter inputs of two processors and to filter the remaining one processor input. 제5항에 있어서, 상기 상태제어수단은 상기 FIFO메모리에 입력되는 정보를 저장하게 하고, 상기 FIFO메모리가 넘치게 되면 정보입력불가신호를 출력하여 타프로세서의 무효화정보가 처리되지 않도록 하는 다중프로세서의 캐시메모리 필터링 장치.The multiprocessor cache of claim 5, wherein the state control means stores information input to the FIFO memory, and outputs an information input disable signal when the FIFO memory overflows to prevent processing of invalidation information of another processor. Memory filtering device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940015666A 1994-06-30 1994-06-30 Cache memory filtering apparatus of multi-processor KR960015583B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008121540A1 (en) * 2007-03-30 2008-10-09 Microsoft Corporation In-memory caching of shared customizable multi-tenant data
US10922229B2 (en) 2019-03-11 2021-02-16 Microsoft Technology Licensing, Llc In-memory normalization of cached objects to reduce cache memory footprint

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008121540A1 (en) * 2007-03-30 2008-10-09 Microsoft Corporation In-memory caching of shared customizable multi-tenant data
US8095618B2 (en) 2007-03-30 2012-01-10 Microsoft Corporation In-memory caching of shared customizable multi-tenant data
US10922229B2 (en) 2019-03-11 2021-02-16 Microsoft Technology Licensing, Llc In-memory normalization of cached objects to reduce cache memory footprint

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