KR960013642B1 - Manufacture of capacitor storage electrode - Google Patents

Manufacture of capacitor storage electrode Download PDF

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Publication number
KR960013642B1
KR960013642B1 KR1019930010498A KR930010498A KR960013642B1 KR 960013642 B1 KR960013642 B1 KR 960013642B1 KR 1019930010498 A KR1019930010498 A KR 1019930010498A KR 930010498 A KR930010498 A KR 930010498A KR 960013642 B1 KR960013642 B1 KR 960013642B1
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South Korea
Prior art keywords
storage electrode
insulating layer
forming
mask
layer
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KR1019930010498A
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Korean (ko)
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KR950002030A (en
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우상호
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현대전자산업 주식회사
김주용
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Priority to KR1019930010498A priority Critical patent/KR960013642B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The method of manufacturing capacitor storage electrode comprises the steps of : forming a word line(5), an insulating layer(7) on a silicone substrate(1), and forming a contact hole for a storage electrode by etching some of the insulating layer(7); forming a first conductive layer(17) for a storage electrode on the insulating layer and on the contact hole, and forming insulating layers(11,13); forming a photoresist pattern(21) for a first storage electrode mask on the insulating layer, and forming an insulating layer pattern(19A) by etching the exposed insulating layer; forming a second conductive layer(23) for a storage electrode and a photoresist pattern(25) for a second storage electrode mask ; forming a hexahedral storage electrode(30) by etching the conductive layers(23,17) of the revealed region; and exposing the inside of the storage electrode(30) by wet etching the insulating layer(19A) inside the storage electrode(30).

Description

캐패시터 저장전극 제조방법Capacitor Storage Electrode Manufacturing Method

제1도는 디램셀의 주요부분을 도시한 레이아웃도.1 is a layout diagram showing main parts of a DRAM cell.

제2도는 내지 제2d도는 본 발명에 의해 6면체 형태의 저장전극을 제조하는 단계를 도시한 단면도.2 to 2d is a cross-sectional view showing a step of manufacturing a storage electrode of the hexagonal form according to the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 3 : 소자분리 산화막1: silicon substrate 3: device isolation oxide film

5 : 워드라인 7 : 제1절연층5 word line 7 first insulating layer

9 : 비트라인 11 : 제2절연층9: bit line 11: second insulating layer

13 : 제3절연층 15 : 감광막패턴13: third insulating layer 15: photosensitive film pattern

17 : 제1도전층 19 : 제4절연층17: first conductive layer 19: fourth insulating layer

21 : 감광막패턴 23 : 제2도전층21: photosensitive film pattern 23: the second conductive layer

25 : 감광막패턴 30 : 저장전극25 photosensitive film pattern 30 storage electrode

50 : 워드라인 마스크 70 : 비트라인 콘택마스크50: word line mask 70: bit line contact mask

80 : 제1저장전극 마스크 90 : 제2저장전극 마스크80: first storage electrode mask 90: second storage electrode mask

100 : 저장전극 콘택마스크100: storage electrode contact mask

본 발명은 고집적 디램셀의 캐패시터 저장전극 제조방법에 관한 것으로, 특히 캐패시터 용량을 증대시키기 위하여 저장전극의 높이는 낮게하면서 표면적을 증대시킬 상부면에 창이 구비된 육면체 형태의 저장전극을 제조하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor storage electrode of a highly integrated DRAM cell, and more particularly, to a method of manufacturing a storage electrode having a hexahedron shape having a window on an upper surface thereof to increase the surface area while lowering the height of the storage electrode in order to increase the capacitor capacity. will be.

반도체 소자가 고집적화 됨에 따라 단위 디램셀당 적용할 수 있는 캐패시터 면적이 줄어들어 셀 동작에 필요한 일정량의 캐패시터 용량을 확보하기 위하여 종래의 3차원적인 캐패시터의 실린더구조는 실린더의 높이를 높여야 하며, 핀구조는 핀의 수를 늘려야 한다. 그러나 이러한 방법은 높이 토폴로지(Topology)로 인해 후속공정의 식각공정 등에 공정상의 어려움을 주게 된다.As semiconductor devices are highly integrated, the capacitor area applicable per unit DRAM cell is reduced, so that the cylinder structure of the conventional three-dimensional capacitor has to increase the height of the cylinder. You must increase the number of. However, this method has a process difficulty due to the height topology and the etching process of the subsequent process.

따라서, 본 발명은 상기한 문제점을 해결하기 위해 캐패시터 저장전극의 높이를 최소화하고, 표면적을 증대시킨 상부면에 창이 구비된 육면체 형태의 캐패시터 저장전극 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor storage electrode having a hexahedron shape having a window on the upper surface of which the height of the capacitor storage electrode is minimized and the surface area is increased in order to solve the above problems.

본 발명에 의하면 실리콘기판 상부에 워드라인이 형성되고 그 상부에 절연층을 형성하고, 상기 절연층의 일정부분을 식각하여 저장전극용 콘택홀을 형성하는 단계와, 저장전극용 제1도전층을 상기 절연층과 콘택홀 상부에 형성하고, 그 상부에 예정된 두께를 갖는 절연층을 형성하는 단계와, 절연층 상부에 제1저장전극 마스크용 감광막패턴을 형성하고, 노출된 절연층을 식각하여 절연층패턴을 형성하고, 제1저장전극 마스크용 감광막패턴을 형성하고, 노출된 절연층을 식각하여 절연층패턴을 형성하고, 제1저장전극 마스크용 감광막패턴을 형성하고, 노출된 절연층을 식각하여 절연층패턴을 형성하고, 제1저장전극 마스크용 감광막패턴을 제거하는 단계와, 저장전극용 제2도전층을 제1도전층과 절연층패턴 상부에 형성하고, 그 상부에 제2저장전극 마스크용 감광막패턴을 형성하는 단계와, 노출된 지역의 제2도전층과 제1도전층을 식각하여, 제1도전층과 제2도전층으로 이루어지고 상부에는 창이 구비된 6면체 구조의 저장전극을 형성하는 단계와, 저장전극 내부에 있는 절연층을 습식식각하여 저장전극 내부면을 노출시키는 단계를 포함하는 것을 특징으로 한다.According to the present invention, a word line is formed on a silicon substrate, an insulating layer is formed on the silicon substrate, and a portion of the insulating layer is etched to form a contact hole for a storage electrode, and a first conductive layer for the storage electrode is formed. Forming an insulating layer having a predetermined thickness on the insulating layer and the contact hole, forming a photoresist pattern for the first storage electrode mask on the insulating layer, and etching the exposed insulating layer to insulate the insulating layer. Forming a layer pattern, forming a photoresist pattern for the first storage electrode mask, etching the exposed insulation layer to form an insulation layer pattern, forming a photoresist pattern for the first storage electrode mask, and etching the exposed insulation layer Forming an insulating layer pattern, removing the photoresist pattern for the first storage electrode mask, and forming a second conductive layer for the storage electrode on the first conductive layer and the insulating layer pattern, and forming a second storage electrode thereon. hemp Forming a photoresist film pattern for the sc; and etching the second conductive layer and the first conductive layer in the exposed area, the storage electrode having a hexagonal structure consisting of a first conductive layer and a second conductive layer and having a window on the top thereof. And forming a wet layer of the insulating layer in the storage electrode to expose the inner surface of the storage electrode.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1도는 디램셀의 주요부분을 도시한 레이아웃도로서, 세로방향으로 배열된 다수의 워드라인 마스크(50), 가로방향으로 배열된 비트라인 마스크(60), 비트라인 콘택마스크(70), 제1저장전극 마스크(80), 제2저장전극 마스크(90) 및 저장전극 콘택마스크(100)가 각각 배치된 것을 도시한다.FIG. 1 is a layout diagram showing main parts of a DRAM cell, wherein a plurality of word line masks 50 arranged in a vertical direction, a bit line mask 60 arranged in a horizontal direction, a bit line contact mask 70, 1 shows that the storage electrode mask 80, the second storage electrode mask 90, and the storage electrode contact mask 100 are disposed.

제2a도 내지 제2d도 본 발명의 실시예에 의해 실리콘기판에 콘택된 저장전극을 제조하는 단계를 제1도의 I-1를 따라 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a step of manufacturing a storage electrode contacted to a silicon substrate according to an exemplary embodiment of the present invention along I-1 of FIG.

제2a도는 실리콘기판(1) 상부에 소자분리 산화막(3)과 워드라인(5)을 형성하고, 그 상부에 제1절연층(7)을 형성하고, 비트라인 콘택마스크를 이용한 식각공정으로 제1절연층(7)을 제거하여 콘택홀을 형성하고, 그 상부에 제2절연층(11)과 제3절연층(13)을 적층하고, 저장전극 콘택마스크용 감광막패턴(15)을 이용하여 상기 제3절연층(13)과 제2절연층(11), 제1절연층(7)을 순차적으로 식각하여 콘택홀을 형성한 단면도이다. 상기 제2절연층(11)과 제3절연층(13)을 예정된 에찬트에서 높은 식각선택비를 갖는 물질을 형성되는데, 제2절연층(11)은 예를들어 PSG(Phospho Silicate Glass)층과 BPSG(Boro Phospho Silcate Glass)으로 형성하고, 제3절연층(13)은 HTO (Middle Temperature Oxide)층 또는 TEOS(Tetra Ethyl Ortho Silicate)층으로 형성할 수 있다.FIG. 2A illustrates an isolation process of forming an isolation layer 3 and a word line 5 on the silicon substrate 1, forming a first insulating layer 7 on the silicon substrate 1, and performing an etching process using a bit line contact mask. 1, the insulating layer 7 is removed to form a contact hole, and the second insulating layer 11 and the third insulating layer 13 are stacked thereon, and the photoresist pattern 15 for the storage electrode contact mask is used. The third insulating layer 13, the second insulating layer 11, and the first insulating layer 7 are sequentially sectional views to form contact holes. The second insulating layer 11 and the third insulating layer 13 may be formed of a material having a high etching selectivity at a predetermined etchant. The second insulating layer 11 may be, for example, a PSG layer. And BPSG (Boro Phospho Silcate Glass), and the third insulating layer 13 may be formed of a HTO (Middle Temperature Oxide) layer or a TEOS (Tetra Ethyl Ortho Silicate) layer.

제2b도는 제2a도 공정후 상기 저장전극 콘택마스크용 감광막패턴(15)을 제거하고, 저장전극용 제1도전층(17) 예를들어 도프된 폴리실리콘층을 증착하고, 그 상부에 제4절연층(19) 예를들어 ,PSG층 BPSG층을 예정된 두꼐(5000∼1000Å)로 형성되고, 제1저장전극 마스크용 감광막패턴(21)을 형성한 단면도이다. 여기서 제1저장전극 마스크는 일반적인 저장전극 마스크보다 일정폭이 작게 형성된다.FIG. 2B shows the photoresist pattern 15 for the storage electrode contact mask after the process of FIG. 2A is removed, and the doped polysilicon layer is deposited on the first conductive layer 17 for the storage electrode. The insulating layer 19 is, for example, a cross-sectional view in which a PSG layer BPSG layer is formed with a predetermined thickness (5000 to 1000 GPa) and a photosensitive film pattern 21 for a first storage electrode mask is formed. Here, the first storage electrode mask is formed to have a predetermined width smaller than that of the general storage electrode mask.

제2c도는 제2b도 공정후 노출된 제4절연층(19)을 식각하여 직6면체 형태의 제4절연층패턴(19a)을 형성하고, 제1저장전극 마스크용 감광막패턴(21)을 제거한 다음, 저장전극용 제2도전층(23) 예를들어 도프된 폴리실리콘층을 형성하고, 그 상부에 제2저장전극 마스크용 감광막패턴(25)을 형성한 단면도이다. 여기서 제2저장전극 마스크는 도시된 바와같이 일반적인 저장전극 마스크와 크기는 같고 중앙부에 창이 형성된다.In FIG. 2C, the fourth insulating layer 19 exposed after the process of FIG. 2B is etched to form a fourth insulating layer pattern 19a having a rectangular parallelepiped shape, and the photoresist pattern 21 for the first storage electrode mask is removed. Next, a cross-sectional view of forming a second conductive layer 23 for a storage electrode, for example, a doped polysilicon layer, and forming a photoresist pattern 25 for a second storage electrode mask thereon. In this case, the second storage electrode mask has the same size as a general storage electrode mask and a window is formed in the center as shown.

제2d도는 제2c도 공정 후에 노출된 저장전극용 제2도전층(23)을 식각하고, 그 하부의 저장전극용 제1도전층(17)을 식각하여 제1도전층(17)과 제2도전층(23)으로 이루어지고 상부에 창이 구비된 직6면체 형태의 저장전극(30)을 형성하고, 저장전극(30) 내부에 있는 제4절연층패턴(19A)을 습식식각으로 제거하여 저장전극(30) 내부표면을 노출시키고, 저부에 있는 제3절연층(13)을 습식식각하여 저장전극(30) 저부면을 노출시킨 것을 도시한 단면사시도이다.In FIG. 2D, the second conductive layer 23 for the storage electrode exposed after the process of FIG. 2C is etched, and the first conductive layer 17 for the storage electrode is etched thereunder to etch the first conductive layer 17 and the second. The storage electrode 30 is formed of a conductive layer 23 and has a window on the upper side thereof, and the fourth insulating layer pattern 19A in the storage electrode 30 is removed by wet etching. The cross-sectional perspective view shows that the inner surface of the electrode 30 is exposed, and the bottom surface of the storage electrode 30 is exposed by wet etching the third insulating layer 13 at the bottom thereof.

상기 제4절연층패턴(19A)을 습식식각할 때 제3절연층(13)이 식각베리어층으로 사용하며, 제3절연층(13)을 습식식각할 때 제2절연층(11)이 식각베리어층으로 사용된다.When the fourth insulating layer pattern 19A is wet etched, the third insulating layer 13 is used as an etch barrier layer, and when the third insulating layer 13 is wet etched, the second insulating layer 11 is etched. Used as a barrier layer.

제2d도의 동정으로 저장전극(30)을 제조하고, 저장전극(30)의 외부 및 내부표면에 캐패시터 유전체막 및 플레이트 전극(도시안됨)을 형성하여 캐패시터를 형성하면 된다.The storage electrode 30 may be manufactured by identifying the capacitor of FIG. 2D, and the capacitor dielectric film and the plate electrode (not shown) may be formed on the outer and inner surfaces of the storage electrode 30 to form the capacitor.

종래의 3차원 구조인 실린더형 저장전극은 상부덮개가 형성되지 않지만 본 발명은 저장전극의 상부덮개가 구비되어 덮개의 상,하부 표면을 캐패시터 유효면적으로 사용할 수 있다. 또한 본 발명에 의한 저장전극 제조공정이 비교적 간단하여 반도체 제조공정에 적용하는에 어려움이 없다.In the conventional three-dimensional cylindrical storage electrode, the upper cover is not formed, but in the present invention, the upper cover of the storage electrode is provided so that the upper and lower surfaces of the cover can be used as the effective capacitor area. In addition, the storage electrode manufacturing process according to the present invention is relatively simple, there is no difficulty in applying to the semiconductor manufacturing process.

Claims (6)

실리콘기판 상부에 워드라인이 형성되고 그 상부에 절연층을 형성하고, 상기 절연층의 일정부분을 식각하여 저장전극용 콘택홀을 형성하는 단계와, 저장전극용 제1도전층을 상기 절연층과 콘택홀 상부에 형성하고, 그 상부에 예정된 두께를 갖는 절연층을 형성하는 단계와, 절연층 상부에 제1저장전극 마스크용 감광막패턴을 형성하고, 노출된 절연층을 식각하여 절연층패턴을 형성하고, 제1저장전극 마스크용 감광막패턴을 제거하는 단계와, 노출된 지역의 제2도전층과 제1도전층을 식각하여, 제1도전층과 지2도전층으로 이루어지고 상부에는 창이 구비된 6면체 구조의 저장전극을 형성하는 단계와,저장전극 내부에 있는 절연층을 습식식각하여 저장전극 내부면을 노츨시키는 단계를 포함하는 캐패시터 저장전극 제조방법.Forming a contact line for a storage electrode by etching a portion of the insulating layer and forming an insulating layer on the silicon substrate, and forming a contact hole for a storage electrode, and forming a first conductive layer for a storage electrode with the insulating layer. Forming an insulating layer having a predetermined thickness on the contact hole, forming a photoresist pattern for the first storage electrode mask on the insulating layer, and etching the exposed insulating layer to form an insulating layer pattern And removing the photoresist pattern for the first storage electrode mask, etching the second conductive layer and the first conductive layer in the exposed area, and including the first conductive layer and the ground conductive layer, and having a window on the upper portion. A method of manufacturing a capacitor storage electrode, the method comprising: forming a storage electrode having a hexagonal structure, and wet etching an insulating layer in the storage electrode to expose an inner surface of the storage electrode. 제1항에 있어서, 워드라인 상부에 형성하는 절연층은 제1 절연층, 제2절연층 및 제3절연층으로 적층하는 것을 특징으로 하는 캐패시터 저장전극 제조방법The method of claim 1, wherein the insulating layer formed on the word line is stacked with a first insulating layer, a second insulating layer, and a third insulating layer. 제1항에 있어서, 상기 제2절연층과 제3절연층은 예정된 에찬트에서 식각선택비가 다른 것을 특징으로 하는 캐패시터 저장전극 제조방법.The method of claim 1, wherein the second insulating layer and the third insulating layer have different etch selectivity at predetermined etchant. 제1항에 있어서, 상기 제1저장전극 마스크는 종래의 저장전극 매스크보다 가장자리에서 일정폭이 작게 형성된 것을 특징으로 하는 캐패시터 저장전극 제조방법.The method of claim 1, wherein the first storage electrode mask has a predetermined width smaller than a conventional storage electrode mask at an edge thereof. 제1항에 있어서, 상기 제2저장전극 마스크는 종래의 저장전극 마스크와 같고 중앙부에는 창이 형성된 것을 특징으로 하는 캐패시터 저장전극 제조방법.The method of claim 1, wherein the second storage electrode mask is the same as a conventional storage electrode mask, and a window is formed at a central portion thereof. 제1항에 있어서, 저장전극 내부에 있는 절연층을 제거한 다음, 저장전극의 저부에 있는 절연층의 일부, 즉 제3절연층을 제거하는 것을 특징으로 하는캐패시터 저장전극 제조방법.The method of claim 1, wherein the insulating layer in the storage electrode is removed, and then a portion of the insulating layer at the bottom of the storage electrode, that is, the third insulating layer is removed.
KR1019930010498A 1993-06-10 1993-06-10 Manufacture of capacitor storage electrode KR960013642B1 (en)

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