KR960012258B1 - Semiconductor device fabrication process - Google Patents

Semiconductor device fabrication process

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Publication number
KR960012258B1
KR960012258B1 KR1019930002328A KR930002328A KR960012258B1 KR 960012258 B1 KR960012258 B1 KR 960012258B1 KR 1019930002328 A KR1019930002328 A KR 1019930002328A KR 930002328 A KR930002328 A KR 930002328A KR 960012258 B1 KR960012258 B1 KR 960012258B1
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South Korea
Prior art keywords
film
nitride film
capacitor
semiconductor device
forming
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KR1019930002328A
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Korean (ko)
Inventor
고재홍
강창석
권기원
선용빈
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삼성전자 주식회사
김광호
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Priority to KR1019930002328A priority Critical patent/KR960012258B1/en
Priority to GB9403144A priority patent/GB2275366B/en
Priority to DE4405250A priority patent/DE4405250A1/en
Priority to CA002115944A priority patent/CA2115944A1/en
Priority to JP6022340A priority patent/JPH06291255A/en
Application granted granted Critical
Publication of KR960012258B1 publication Critical patent/KR960012258B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)

Abstract

The method of fabricating semiconductor device comprises the steps of : forming a first conducting layer(20) on a semiconductor substrate; forming a nitridef film(23) on the first conducting layer(20); ozone(O3) processing of the nitridef film(23). The method improves the quality of the nitrided film.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제1a도 및 제1b도는 종래 NO 구조의 유전체막을 구비한 커패시터의 형성 방법을 나타낸 공정 순서도,1A and 1B are process flowcharts showing a method of forming a capacitor having a dielectric film having a conventional NO structure,

제2a도 내지 제2c도는 본 발명에 따른 커패시터 형성 방법의 일실시예를 나타낸 공정 순서도,2a to 2c is a process flowchart showing an embodiment of a capacitor forming method according to the present invention,

제3도는 본 발명에 따른 커패시터 형성 방법의 다른 실시예를 통해 형성된 커패시터의 구조를 나타낸 단면도,3 is a cross-sectional view showing a structure of a capacitor formed through another embodiment of a capacitor forming method according to the present invention;

제4도는 본 발명에 따른 커패시터 형성 방법의 또 다른 실시예를 통해 형성된 커패시터의 구조를 나타낸 단면도,4 is a cross-sectional view showing the structure of a capacitor formed through another embodiment of the method for forming a capacitor according to the present invention;

제5도는 본 발명의 실시예를 통하여 형성된 커패시터의 전류밀도-인가전계(J-E) 곡선을 나타낸 그래프,5 is a graph showing a current density-applied electric field (J-E) curve of a capacitor formed through the embodiment of the present invention;

제6도는 상기 제5도에 도시된 각각의 J-E 곡선의 오존 처리 공정 조건을 나타낸 도표이다.FIG. 6 is a chart showing ozone treatment process conditions of each J-E curve shown in FIG.

본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 오존 처리된 질화막을 갖는 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having an ozonated nitride film.

최근 반도체 제조 기술의 발달과 메모리 소자의 응용 분야가 확장되어 감에 따라 대용량의 메모리 소자개발이 진척되고 있는데, 특히 1개의 메모리 셀(cell)을 1개의 커패시터와 1개의 트랜지스터로 구성함으로써 고집적화에 유리한 DRAM(Dynamic Random Access Memory)의 괄목할 만한 발전이 이루어져 왔다.Recently, as the development of semiconductor manufacturing technology and the application field of memory devices are expanded, the development of large-capacity memory devices is progressing. Especially, one memory cell is composed of one capacitor and one transistor, which is advantageous for high integration. Significant advances have been made in Dynamic Random Access Memory (DRAM).

이 DRAM의 개발은 3년에 4배의 고집적화를 달성하게 되었는데, 현재 DRAM의 집적도는 2Mb DRAM이 양산 단계에 접어들었고, 16Mb와 64Mb는 양산을 향해 빠른 속도로 개발이 진행 중이며, 64Mb 및 256Mb는 개발을 위한 연구가 활발히 진행되고 있다.The development of this DRAM has achieved four times higher integration in three years. Currently, the density of DRAM is in mass production with 2Mb DRAM, and 16Mb and 64Mb are rapidly developing toward mass production, while 64Mb and 256Mb Research for development is actively underway.

이러한 반도체 메모리 장치는 정보의 독출과 저장을 위해 큰 정전 용량을 가져야 하는데, 집적도가 4배 증가할 때 침(chip) 면적이 1.4배의 증가에 그침으로써 상대적으로 메모리 셀의 면적은 1/3배 줄어들게 되어, 기존의 커패시터 구조로써는 한전된 면적내에서 충분히 큰 셀 커패시턴스를 확보할 수 없다. 따라서 작은 면적내에서 보다 큰 커패시턴스를 얻기 위한 방법의 연구가 요구되었는데, 이 방법은 보통 다음의 3가지로 나뉘어질 수 있다. 즉, 첫째는 유전체막의 두께 감소, 둘째는 커패시터의 유효면적 증가, 셋째는 유전 상수가 큰 물질의 사용이 그것이다.Such a semiconductor memory device must have a large capacitance for reading and storing information. When the density increases by 4 times, the chip area increases by 1.4 times, so that the area of the memory cell is 1/3 times that of the memory cell. As a result, the existing capacitor structure cannot secure sufficiently large cell capacitance in the isolated area. Therefore, a study of a method for obtaining a larger capacitance in a small area was required. This method can be generally divided into three types. That is, firstly, the thickness of the dielectric film is reduced, secondly, the effective area of the capacitor is increased, and thirdly, the use of a material having a large dielectric constant.

이중에서 세번째의 경우, 메모리 소자의 집적도가 증가함에 따라 작은 메모리 셀 면적내에 큰 유전 용량을 확보하기 위하여 고유전물질이나 강유전물질을 커패시터용 유전체막으로 사용하던가, 유전체막의 구조를 통상적으로 사용되던 산화막의 단일층 구조에서 질화막/산화막(Nitride/Oxide ; 이하, NO라 칭함)구조, 혹은 산화막/질화막/산화막(Oxide/Nitrid/Oxide ; 이하, ONO라 칭함) 구조등으로 변경하여 사용하는 것이다.In the third and third cases, as the degree of integration of memory devices increases, high dielectric or ferroelectric materials are used as the dielectric films for capacitors or the dielectric films are commonly used to secure large dielectric capacity in a small memory cell area. It is used by changing from a single layer structure to a nitride film / oxide film (hereinafter referred to as NO) structure or an oxide film / nitride film / oxide film (hereinafter referred to as ONO) structure.

제1a도 및 제1b도는 종래 NO 구조의 유전체막을 구비한 커패시터의 형성 방법을 나타낸 공정순서도이다.1A and 1B are process flowcharts showing a method of forming a capacitor having a dielectric film having a conventional NO structure.

제1a도는 유전체막(13)의 형성 단계를 도시한 것으로, 커패시터의 제1전극으로 사용되는 제1도전층(10), 예컨대 불순물이 도우핑된 다결정 실리콘을 질화(nitridation)시킨 후에 저압화학기상증착(Low Pressure Chemical Vapor Doposition ; 이하, LPCVD라 칭함)법으로 20Å∼200Å 정도의 산화막(13b)을 형성하여 질화막/산화막 구조의 유전체막(13)을 형성한다. 이때, 상기 산화막(3b)을 형성하는데 필요한 온도는 850℃ 정도이다.FIG. 1A shows the step of forming the dielectric film 13, wherein the first conductive layer 10 used as the first electrode of the capacitor, such as polycrystalline silicon doped with impurities, is nitrided and then subjected to low pressure chemical vapor phase. An oxide film 13b of about 20 kPa to 200 kPa is formed by a low pressure chemical vapor deposition (LPCVD) method to form a dielectric film 13 having a nitride film / oxide film structure. At this time, the temperature required to form the oxide film 3b is about 850 ° C.

제1b도는 상기 제1a도 단계 이후, 상기 산화막(13b)위에 커패시터의 제2전극으로 사용되는 제2전도층(15), 예컨대 불순물이 도우핑된 다결정 실리콘을 50Å∼500Å 정도의 두께로 형성함으로써 커패시터의 제작을 완성하는 단계를 나타낸다.FIG. 1B is formed by forming a second conductive layer 15 used as a second electrode of a capacitor on the oxide film 13b, for example, polycrystalline silicon doped with impurities, to a thickness of about 50 kV to 500 kV after the FIG. The steps to complete the fabrication of the capacitor are shown.

상술한 바와 같은 NO 구조의 유전체막을 구비한 커패시터의 제조방법에서 사용되는 질화막은 유전 상수가 약7로서 산화막의 유전 상수 3.8에 비하여 유전 상수가 큰 장점이 있지만, 상기 질화막의 형성시 LPCVD법의 도포 특성 때문에 막질 자체가 핀 호울(pin hole)이나 결정 결함 또는 불순물 편석에 의한 결함들을 포함하게 된다. 따라서 막의 질이 떨어지게 되고, 누설 전류가 크므로 상기 질화막 도포 후에 이 질화막의 표면을 산화시켜 NO 구조의 유전체막을 사용하게 되었는데, 이와 같은 종래의 기술은 850℃ 정도에서, 30분의 산화 과정을 반드시 거쳐야 하는 단점을 가지고 있어서 반도체 메모리 소자가 고집적화됨에 따라 요구되는 얕은 접합(shallow junction)의 형성을 어렵게 한다. 또한, 종래의 기술은 NO 구조 유전체막의 유효산화막 두께(Tox)가 약 40Å이 그 한계라고 알려져 있으므로 256Mb 이상의 고집적 메모리 소자에 NO 구조 유전체막을 적용하기에는 커패시터 구조가 3차원적으로 복잡해지지 않으며 안되는 문제점이 발생하게 된다.The nitride film used in the method of manufacturing a capacitor having a dielectric film having a NO structure as described above has a dielectric constant of about 7 and a great advantage over the dielectric constant 3.8 of the oxide film. Due to their properties, the film itself contains pin holes, crystal defects or defects due to impurity segregation. Therefore, since the quality of the film is reduced and the leakage current is large, the surface of the nitride film is oxidized after the application of the nitride film to use a dielectric film having a NO structure. The disadvantage of having to go through is that it is difficult to form a shallow junction required as the semiconductor memory device is highly integrated. In addition, the conventional technique is known that the limit of effective oxide thickness (Tox) of the NO structure dielectric film is about 40 [mu] s. Therefore, there is a problem that the capacitor structure is not complicated in three dimensions to apply the NO structure dielectric film to the highly integrated memory device of 256 Mb or more. Will occur.

본 발명의 목적은 상기한 바와 같은 종래 기술의 문제점을 해결하기 위하여 질화막의 막질을 개선시킬 수 있는 단계를 추가함으로써, 상기 질화막을 구비하는 반도체 장치의 특성을 개선시킬 수 있는 반도체 장치의 제조 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the characteristics of a semiconductor device including the nitride film by adding a step of improving the film quality of the nitride film in order to solve the problems of the prior art as described above. To provide.

상기 목적을 달성하기 위하여, 본 발명은 반도체 기판상에 하지막을 형성하는 단계와, 상기 하지막상에 질화막을 형성하는 단계와, 상기 질화막을 오존처리하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조방법에 제공한다.In order to achieve the above object, the present invention includes the steps of forming a base film on a semiconductor substrate, forming a nitride film on the base film, and ozone treatment of the nitride film. To give way.

상기 하지막은 도전막으로 형성할 수 있다.The base film may be formed of a conductive film.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 설명하기로 한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

제2a도 내지 제2c도는 본 발명에 따른 커패시터 형성 방법의 일실시예를 나타낸 공정순서도이다.2a to 2c is a process flow diagram showing an embodiment of a capacitor forming method according to the present invention.

제2a도는 질화막(23)의 형성 단계를 도시한 것으로, 먼저 커패시터의 제1전극으로 사용되는 제1도전층(20), 예컨대 면저항이 10Ω∼100Ω/n인 불순물이 도우핑된 다결정 실리콘을 50Å∼5000Å 정도의 두께로 형성한다. 이어서 상기 다결정 실리콘을 질화시킨 후, LPCVD법으로 20Å∼200Å 두께의 질화막(23)을 도포한다.FIG. 2A shows a step of forming the nitride film 23. First, the first conductive layer 20 used as the first electrode of the capacitor, for example, 50 Å of polycrystalline silicon doped with impurities having a sheet resistance of 10 Ω to 100 Ω / n It is formed to a thickness of about -5000Å. Subsequently, after nitriding the polycrystalline silicon, a nitride film 23 having a thickness of 20 kPa to 200 kPa is applied by LPCVD.

제2b도는 상기 제2a도 단계 이후, 상기 질화막에 256nm 혹은 185nm의 자외선을 조사하면서, 50∼300g/nm3의 오존농도, 200℃∼400℃의 기판온도 범위에서, 0.1∼100분의 시간동안 오존처리를 실시하는 단계를 나타낸다. 여기서, 미설명부호 23는 오존처리된 질화막을 나타낸다.FIG. 2b is a ozone concentration of 50 to 300 g / nm 3 and a substrate temperature range of 200 to 400 ° C. for 0.1 to 100 minutes while irradiating 256 nm or 185 nm ultraviolet rays to the nitride film after the step 2a. An ozone treatment step is shown. Here, reference numeral 23 denotes an ozonated nitride film.

제2c도는 상기 제2b도 단계 이후, 결과물 전명에 커패시터의 제2전극으로 사용되는 제2도전층(25), 예컨대 불순물이 도우핑된 다결정 실리콘을 형성함으로써 커패시터의 제작을 완성하는 단계를 나타낸다.FIG. 2C illustrates the step of completing the fabrication of the capacitor by forming the second conductive layer 25 used as the second electrode of the capacitor, such as polycrystalline silicon doped with impurities, in the resultant light after the FIG. 2B step.

여기서, 상기 질화막에 있어서의 오존의 효과를 살펴보면 다음과 같다. 먼저 아래의 식에서 보는 것처럼 오존은 200℃∼300℃의 온도에서 자외선에 의해 분해되어 산소중(oxygen radicals)을 형성한다(제26회 VLSI FORUM, 동경농대 공학부, '광 CVD에 의한 Ta2o5막의 형성과 활성산소 Anneal').Here, the effects of ozone on the nitride film are as follows. First, as shown in the equation below, ozone is decomposed by ultraviolet light at a temperature of 200 ° C to 300 ° C to form oxygen radicals (26th VLSI FORUM, Tokyo University of Agriculture, Ta 2 O 5 Membrane formation and free radicals Anneal ').

O2+hv(185nm)→O(3P)+O(3P)O 2 + hv (185 nm) → O ( 3 P) + O ( 3 P)

O(3P)+O2+O2→1O3+O2 O ( 3 P) + O 2 + O 2 → 1 O 3 + O 2

O2+hv(254nm)→O(1D)+O(1△)O 2 + hv (254 nm) → O ( 1 D) + O ( 1 △)

LPCVD법에 의하여 증착된 Ta2O5막의 경우는 탄탈륨(Ta)이 풍부한 상태로 존재하여, 산소의 공공(空孔 : vacancy)이 있게 되는데, 이것이 누설전류의 역할을 한다. 위의 식에 의하여 생성된 산소종(1D등)이 Ta2O5막으로 확산하여 산소 공공을 치유하는 역할을 한다. 이 경우, 산소종들은 아주 반응성이 크므로 200℃∼300℃의 온도에서도 Ta2O5막의 막질을 현저히 개선시킨다는 것이 Shinriki등의 연구로 밝혀져 있다(H.Shinriki etal. Proc. 46th Annu. Dev. Res. Conf., IEEE Ⅲ-7, 1998).In the case of the Ta 2 O 5 film deposited by the LPCVD method, it exists in a state rich in tantalum (Ta), and there is a vacancy of oxygen, which serves as a leakage current. Oxygen species (D 1 etc.) generated by the above formula is serves to cure the oxygen vacancies to diffuse into the Ta 2 O 5 film. In this case, since oxygen species are very reactive, it has been shown by Shinriki et al. That the film quality of Ta 2 O 5 film is remarkably improved even at a temperature of 200 ° C. to 300 ° C. (H. Shinriki et al. Proc. 46th Annu. Dev. Res. Conf., IEEE III-7, 1998).

이러한 오존의 효과를 질화막의 경우에서도 생각할 수 있는데, 질화막의 핀 호울은 질화막의 도포과정에서 생긴 결함 또는 질화막의 비화학양론성(nonstoichiometry)에 의해 생성된 질화막(Si3N4)의 구조에서 실리콘(Si) 혹은 질소(N)의 공공들이 모여 형성된 것이라고 볼 수 있다.The effect of ozone can be considered in the case of nitride film, but the pin hole of the nitride film is a silicon in the structure of the nitride film (Si 3 N 4 ) generated by defects in the coating process or nonstoichiometry of the nitride film. It can be said that pores of (Si) or nitrogen (N) are formed by gathering.

이러한 질화막의 공공 혹은 결함들이 포획위치(trap site)가 되어 질화막의 누설전류 증가시키는 역할을 한다는 사실은 'Physics of Semiconductor Devices' pp.402∼407을 참고하면 알 수 있다. 따라서 이 핀 호울은 질화막의 다른 부분보다는 산소의 확산계수가 크며, 활성화되어 있다. 따라서 오존처리 과정중에 산소종(radical)이 질화막속을 확산하여 질화막의 공공을 치환하는 역할을 한다고 볼 수 있어서 질화막의 막질을 개선할 수 있다.The fact that the cavities or defects in the nitride film serve as a trap site increases the leakage current of the nitride film and can be known by referring to 'Physics of Semiconductor Devices' pp. 402 to 407. Therefore, this fin hole has a larger diffusion coefficient of oxygen than other parts of the nitride film and is active. Therefore, the oxygen species (radical) diffuses in the nitride film during the ozone treatment process to replace the vacancies of the nitride film can improve the film quality of the nitride film.

상술한 일실시예에서는 커패시터의 유전체막으로 오존처리된 질화막만을 단일층으로 형성하였지만, 다른 실시예로 제3도에 도시된 바와 같이 상기 오존처리된 질화막(23')위에 산화막(24)을 형성함으로써 오존처리된 질화막/산화막 구조의 유전체막을 형성할 수도 있으며, 또한 산화막/질화막/산화막의 삼층 구조의 유전체막을 형성하는 것도 가능하다. 여기서, 상기 산화막(24)의 형성 방법은 종래 일반적인 NO 구조의 산화막 형성 방법과 동일하다. 또다른 실시예로서 제4도에 도시된 바와 같이, 오존처리된 질화막(23')의 상부 및 하부에 산화막(24a),(24b)을 형성함으로써, 산화막/질화막/산화막의 상층 구조의 유전체막을 형성하는 것도 가능하다.In the above-described embodiment, only a nitride layer ozonated as the dielectric film of the capacitor is formed as a single layer, but in another embodiment, an oxide layer 24 is formed on the ozonized nitride film 23 'as shown in FIG. As a result, a dielectric film having an ozone-treated nitride film / oxide film can be formed, and a dielectric film having a three-layer structure of oxide film / nitride film / oxide film can also be formed. Here, the formation method of the oxide film 24 is the same as the conventional oxide film formation method of the general NO structure. As another embodiment, as shown in FIG. 4, by forming the oxide films 24a and 24b on the upper and lower portions of the ozonated nitride film 23 ', the dielectric film of the upper structure of the oxide film / nitride film / oxide film is formed. It is also possible to form.

또 다른 실시예로, 질화막이 보호막(passivation layer)으로 사용되는 경우에 질화막내의 결함들은 수분 혹은 기타 불순물들이 오염이 되는 통로 역할을 할 수 있기 때문에, 이 경우에도 질화막의 도포 후에 오존처리를 실시하면 보호 특성이 개선될 수 있다.In another embodiment, when the nitride film is used as a passivation layer, defects in the nitride film may serve as a path for contamination of moisture or other impurities. Protective properties can be improved.

또한, 본 발명은 상기 커패시터의 유전체막 및 반도체 장치의 보호막에만 적용하는데 그치지 않고, 본 발명의 기술적 사상이 한정하는 범위내로 확장하여 적용할 수 있음은 물론이다.In addition, the present invention is not only applicable to the dielectric film of the capacitor and the protective film of the semiconductor device, but can of course be extended to the extent limited by the technical idea of the present invention.

제5도는 본 발명의 실시예를 통하여 형성된 커패시터의 전류밀도-인가전계(J-E) 곡선을 나타낸 그래프이고, 제6도는 상기 제5도에 도시된 각각의 J-E 곡선의 오존처리 공정 조건을 나타낸 도표이다. 여기서, 상기 제5도에 나타난 결과는 질화막을 70±5Å의 두께로 도포해준 경우이다.5 is a graph showing the current density-applied electric field (JE) curve of the capacitor formed through the embodiment of the present invention, Figure 6 is a chart showing the ozone treatment process conditions of each JE curve shown in FIG. . Here, the result shown in FIG. 5 is a case where the nitride film is applied to a thickness of 70 ± 5Å.

상기 제5도 및 제6도를 살펴보면, 질화막에 오존처리 단계만을 실시한 경우 누설전류와 파괴전압은 종래 질화막위에 산화막을 형성하여준 경우와 비슷한 수준의 값을 나타낸다(종래 방법에 의한 NO 구조 커패시터의 누설전류 곡선은 상기 제5도의 ④,⑤번과 비슷한 값임). 한편, 오존처리된 질화막 위에 종래 방법과 같은 조건하에서 산화막을 형성한 경우에 2∼3오더(order)의 누설전류 감소가 나타나고 파괴전압은 약 2 MV/cm가 증가함을 알 수 있다. 따라서 본 발명의 오존처리 단계는 질화막을 유전체막으로 사용하는 커패시터의 전기적인 특성을 개선시키는데에 큰 효과가 있음을 알 수 있다.Referring to FIGS. 5 and 6, when only the ozone treatment step is performed on the nitride film, the leakage current and the breakdown voltage show values similar to those in the case where an oxide film is formed on the conventional nitride film. Leakage current curve is similar to ④, ⑤ in Fig. 5). On the other hand, when the oxide film is formed on the ozonated nitride film under the same conditions as in the conventional method, it can be seen that the leakage current of 2 to 3 orders appears and the breakdown voltage increases by about 2 MV / cm. Therefore, it can be seen that the ozone treatment step of the present invention has a great effect in improving the electrical characteristics of the capacitor using the nitride film as the dielectric film.

상술한 바와 같이 본 발명은 좋은 막질을 갖는 질화막을 저온에서 오존처리 단계를 통하여 형성할 수 있어서, 오전처리된 질화막을 커패시터에 적용하면 종래 NO 구조와 같이 산화막 형성을 위한 산화 공정 없이도 커패시터를 형성할 수 있다. 또한, 상기 NO 커패시터의 오존처리 단계를 실시한 후 종래 방법과 같은 산화막 형성 단계를 진행하면, 종래 NO 구조에 비하여 누설전류가 현저히 감소할 뿐만 아니라 파괴전압이 증가하여 NO 구조 유전체막의 박막화 한계를 더욱 낮출 수 있다.As described above, the present invention can form a nitride film having a good film quality at a low temperature through an ozone treatment step, so that applying an am treated nitride film to a capacitor can form a capacitor without an oxidation process for forming an oxide film as in a conventional NO structure. Can be. In addition, when performing the oxide film forming step as in the conventional method after performing the ozone treatment step of the NO capacitor, the leakage current is significantly reduced as well as the breakdown voltage is increased as compared with the conventional NO structure, thereby lowering the thinning limit of the NO structure dielectric film Can be.

결과적으로, 본 발명의 반도체 장치의 제조방법은 질화막의 막질을 개선함으로써 질화막을 이용하는 커패시터 등에 적용하여 반도체 장치의 누설전류 및 파괴전압을 증가시킬 수 있다.As a result, the manufacturing method of the semiconductor device of the present invention can increase the leakage current and breakdown voltage of the semiconductor device by applying to a capacitor using a nitride film by improving the film quality of the nitride film.

Claims (5)

반도체 기판상에 하지막을 형성하는 단계 ; 상기 하지막상에 질화막을 형성하는 단계 ; 및 상기 질화막을 오존처리하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조 방법.Forming a base film on the semiconductor substrate; Forming a nitride film on the underlayer; And ozone treatment of the nitride film. 제1항에 있어서, 상기 오존처리 단계는, 상기 질화막에 256nm혹은 185nm의 자외선을 조사하면서, 50∼300g/nm3의 오존농도, 200℃∼500℃의 기판온도 범위에서, 0.1∼100분의 시간동안 실시하는 것을 특징으로 하는 반도체 장치의 제조방법.According to claim 1, The ozone treatment step, while irradiating the ultraviolet light of 256nm or 185nm to the nitride film, the ozone concentration of 50 ~ 300g / nm 3 , the substrate temperature range of 200 ℃ to 500 ℃, 0.1 to 100 minutes A method for manufacturing a semiconductor device, which is carried out for a time. 제1항에 있어서, 상기 오존처리 단계 후, 상기 질화막위에 산화막을 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, further comprising forming an oxide film on the nitride film after the ozone treatment step. 제3항에 있어서, 상기 질화막의 하부에 산화막을 형성하는 공정을 더 구비하는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 3, further comprising a step of forming an oxide film under the nitride film. 제1항에 있어서, 상기 하지막은 도전막인 것을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the base film is a conductive film.
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DE4405250A DE4405250A1 (en) 1993-02-19 1994-02-18 Semiconductor component and method for its production
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