KR960012246B1 - Method for forming a semiconductor device - Google Patents

Abstract

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Description

Method of forming isolation region between elements of semiconductor device

1 is a cross-sectional view of a conventional npn bipolar transistor using a full dielectric isolation method.

(A), (b) and (c) of FIG. 2 are sectional drawing which shows the formation process of the isolation region between elements conventionally.

(A)-(e) of FIG. 3 is sectional drawing which shows the formation process of the isolation | separation area | region between elements of this invention.

* Explanation of symbols for main parts of the drawings

101,201,301: semiconductor substrate 102,105,202,302: insulating film

103,203,303: n ⁺ type buried layer 104,204,304: n type collector region

205,305: resist or silicon oxide film

206,306: groove (trench) by anisotropic etching

107,108,207,310: silicon oxide film 208,308: upper corner of trench

209,309: lower trench corner 210: crystal defect occurring at lower trench corner

106,311 polycrystalline silicon film 110: p ⁺ type graft base region

112 n ⁺ emitter region 113 emitter electrode

114: base electrode 115: collector electrode

The present invention relates to a method for forming an isolation region between elements of a semiconductor integrated circuit device for use in high speed operation circuits, high breakdown voltage circuits, and the like.

A complete dielectric separation technique in which a semiconductor layer is formed on an insulating film and a device is formed on the semiconductor layer has high reliability such as high speed operation due to reduction of parasitic capacitance, high breakdown voltage, or high latch up. There is an advantage.

1 is an example of a fast bipolar integrated circuit using a full dielectric isolation technique. The n layer 104 and the n + layer 103 serving as the collector region are separated from the substrate 101 by the insulating film 102, and are separated from the adjacent elements by the insulating film 105 of the trench isolation. The parasitic capacitance between the collector and the substrate is significantly reduced and the circuit operation is faster than when separated by the pn junction.

2A to 2C are cross-sectional views showing the step of forming the trench isolation portion of the fast bipolar transistor using the full dielectric isolation technique. First, a silicon layer including an n + layer 203 and an n layer 204 is formed on the silicon insulating film 202 as shown in FIG. The formation method is a method of performing hydrophilic treatment on the silicon insulating film 202 and the silicon layer, followed by bonding and heat treatment (JP-A-62-27040), melt recrystallization by laser or electron beam, and implantation of O ⁺ ions. To form an oxide film layer.

Next, the anisotropic groove 206 is formed by the reactive ion etching using a gas such as CBrF ₃ using a resist or a silicon oxide film 205 patterned by a conventional lithography method as a mask. Form as shown in b). Next, by thermal oxidation, a silicon oxide film 207 is formed on the inner wall of the trench (see FIG. 2C).

Trench corner portions 208 and 209 are subjected to large stresses during oxidation, resulting in thinning of the oxide film, and thus causing crystal defects. As a countermeasure, there is a method of cutting off and rounding the upper corner convex portion 208 by chemical dry etching. However, the lower corner portion 209 is not rounded at this time. On the other hand, the defect generated in the lower corner portion 209 grows in the upward direction of the inclination of 45 °, so that the probability of reaching the surface is increased, which greatly reduces the yield of the device. The present invention is to solve such a problem, and relates to a method of forming an oxide film in the trench inner wall when the trench isolation is used for the isolation between devices formed in the single crystal semiconductor layer formed on the insulating film, the trench lower corner The purpose is to prevent crystal defects from developing toward the surface of the device.

A method of forming an isolation region between elements of a semiconductor device according to the present invention includes forming a groove reaching an insulating film by using anisotropic etching in a single crystal semiconductor layer formed on the insulating film, and using the wet or dry etching. Removing the polymer and the damage layer during the etching process, forming a polycrystalline semiconductor film in the groove by using a reduced pressure gas phase growth method, and oxidizing the polycrystalline semiconductor film and the single crystal semiconductor layer in contact with each other by thermal oxidation. And forming an oxide film.

When the insulating film is formed on the inner wall of the trench isolation formed on the single crystal semiconductor layer formed on the insulating film, the corners are rounded by depositing the polycrystalline semiconductor film by a reduced pressure vapor phase growth method in advance, and then a thermal oxide film is formed on the insulating film. Prevents crystal defects that develop into the surface from the adjacent lower corner of the trench.

(Example)

As an embodiment of the present invention, a step of forming an isolation region between elements of an npn type bipolar transistor will be described with reference to the cross-sectional view of FIG.

First, as shown in FIG. 3A, a single crystal semiconductor layer including n ⁺ region 303 and n region 304 for extracting collector electrodes is formed on an insulating film 302 such as a silicon oxide film. This formation method, as shown in the prior art, completes the crystallinity of the single crystal semiconductor layers 303 and 304 such as a wafer bonding technique, a melt recrystallization method by a laser or electron beam, and an oxide film formation method by O ⁺ ion implantation. If it does not reduce, it is possible.

Next, as shown in FIG. 3 (b) as an isolation region between elements by a reactive ion etching method using a gas such as CBrF ₃ as a mask using a resist or silicon oxide film 305 patterned by a conventional lithography method as a mask. The groove 306 reaching the insulating film 302 is formed. After the polymer and the damage layer are removed by wet or dry etching, the polycrystalline silicon film 307 is deposited from about 1000 mW to about 2000 mW by the reduced pressure gas phase growth method (see FIG. 3C). At this time, the polycrystalline silicon film is deposited with curvature not only at the upper corner portion 308 but also at the lower corner portion 309, and the upper corner portion 308 and the lower corner portion 309 are formed in FIGS. 3C and 3D. Is indicated by a dotted circle.

Further, a thermal oxidation film 310 of 1000 kPa or more is formed by a hydrogen combustion method at a temperature of about 900 ° C to 1000 ° C (see (d) of FIG. 3). At this time, since the silicon oxide film having a curvature is formed in the lower corner portion 309 and the upper corner portion 308, it is possible to prevent crystal defects that develop from the lower corner portion 309 to the wafer surface, and to significantly improve the yield of the device. Can be raised. In addition, the polycrystalline silicon film 311 and the like are filled by the vacuum vapor deposition method, and this is covered with the silicon oxide film 312 to complete the isolation region between the elements (see FIG. 3E).

As is apparent from the above description, the trench isolation formation method used for the complete dielectric separation of the present invention forms a rounded corner portion in contact with the lower insulating film, so that crystal defects, which have occurred easily at this corner portion, can be prevented. This crystal defect develops in the surface direction of the semiconductor layer, which has been a cause of increase in conventional device yield, but can be greatly improved.

Claims (1)

Forming grooves 306 reaching the insulating film 302 by anisotropic etching in the single crystal semiconductor layers 303 and 304 formed on the insulating film 302; Removing the polymer and the damage layer during the anisotropic etching process using wet or dry etching; Forming a polycrystalline semiconductor film 307 in the groove 306 by using a reduced pressure gas phase growth method; Forming an oxide film (310) by oxidizing the polycrystalline semiconductor film (307) and the single crystal semiconductor layer (303,304) in contact with it by thermal oxidation.