KR960011647B1 - Dram manufacture - Google Patents
Dram manufacture Download PDFInfo
- Publication number
- KR960011647B1 KR960011647B1 KR1019920021019A KR920021019A KR960011647B1 KR 960011647 B1 KR960011647 B1 KR 960011647B1 KR 1019920021019 A KR1019920021019 A KR 1019920021019A KR 920021019 A KR920021019 A KR 920021019A KR 960011647 B1 KR960011647 B1 KR 960011647B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- node
- substrate
- dram
- node pattern
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract 2
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 210000004027 cell Anatomy 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004321 preservation Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 210000004692 intercellular junction Anatomy 0.000 description 1
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1도는 종래 디램의 제조를 설명하기 위한 단면도.1 is a cross-sectional view for explaining the manufacture of a conventional DRAM.
제2도는 본 발명의 디램의 제도를 설명하기 위한 단면도.2 is a cross-sectional view for explaining the system of the DRAM of the present invention.
제3도 및 제4도는 제2도의 누설전류를 설명하기 위한 그래프.3 and 4 are graphs for explaining the leakage current of FIG.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 기판 2 : 필드산화막1 substrate 2 field oxide film
7 : 노드 8 : 플레이트7: Node 8: Plate
본 발명은 디램(DRAM) 제조에 관한 것으로, 특히 누설전류(Leakage Current)를 억제할 수 있는 디램 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DRAM, and more particularly, to a DRAM manufacturing method capable of suppressing leakage current.
일반적으로, 디램은 전하축전량보존이 소자특성유지를 위해 중요하며 전하를 안정적으로 보존하려면 누설전류가 발생하지 않도록 해야 한다.In general, DRAMs are important for the preservation of device characteristics and for the stable preservation of charges, the leakage current should not occur.
종래의 일실시예는 제1도와 같이 가판(P형 실리콘)(1)위 상부 양측에 필드산화막(Field Oxide)(2)을 성장하고, 표면에 게이트 산화막과 게이트 그리고 절연체 형성 공정을 하여 게이트 라인(5)을 형성한 후 노드 접합영역(Node Junction Region)(3)과 비트라인 접합영역(Bit Line Junction Region)(4)의 게이트 산화막과 절연체를 제거한다.A conventional embodiment is to grow a field oxide (2) on both sides of the upper plate (P-type silicon) (1), as shown in Figure 1, the gate oxide film, the gate and the insulator forming process on the surface of the gate line After forming (5), the gate oxide film and insulator of the node junction region 3 and the bit line junction region 4 are removed.
다음, 비트라인(6)을 형성한 후 노드(폴리실리콘)(7), 유전체, 플레이트(Plate)(8)를 차례로 형성한다.Next, after the bit line 6 is formed, a node (polysilicon) 7, a dielectric, and a plate 8 are sequentially formed.
그러나, 이와같은 종래의 기술에 있어서는 소자의 고집적화가 이루어짐에 따라 설(cell) 누설전류가 증가하여 64M DRAM급에서 요구하는 0.2fA/cell 이하의 셀 접합 누설전류를 만족시킬 수 없다.However, in such a conventional technology, as the device is highly integrated, the cell leakage current increases, so that the cell junction leakage current of 0.2 fA / cell or less required by the 64M DRAM class cannot be satisfied.
본 발명은 이와같은 종래의 결점을 감안하여 안출한 것으로, 노드형성을 위한 폴리실리콘을 증착한 후 수소분위기에서 열처리하여 누설전류를 억제할 수 있는 디램 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in view of the above-mentioned drawbacks, and an object thereof is to provide a DRAM manufacturing method capable of suppressing leakage current by depositing polysilicon for forming a node and then performing heat treatment in a hydrogen atmosphere.
이하에서 이와같은 목적을 달성하기 위한 본 발명의 일실시예를 첨부된 도면에 의하여 설명하면 다음과 같다.Hereinafter, described with reference to the accompanying drawings an embodiment of the present invention for achieving the above object.
제2도는 본 발명의 단면도로, 기판(1)의 양측에 필드산화막(2)을 형성한 후 표면에 노드(7)를 패터닝(Patterning)하고, 수소와 질소의 번위기(Forming Gas)에서 400℃~450℃의 온도로 30분~60분간 열처리 한다.2 is a cross-sectional view of the present invention, after forming the field oxide film (2) on both sides of the substrate (1) and patterning the node (7) on the surface (400) in the gas (Forming Gas) of hydrogen and nitrogen (Forming Gas) Heat-treat for 30 to 60 minutes at a temperature of ℃ ~ 450 ℃.
다음, 노드(7) 표면에 유전체, 플레이트(8)를 차례로 증착한다.Next, a dielectric material and a plate 8 are deposited in order on the surface of the node 7.
이와같은 본 발명을 제3, 4도를 참조하여 보면 제3도와 같이 400℃~450℃에서 N2HN2의 분위기로 30분동안 열처리시 A와 같은 상기 열처리를 실시하지 않았을 때보다 B와 같이 상기 열처리를 실시했을 때 셀의 접합 누설전류가 훨씬 작음을 알 수 있고, 제4도와 같이 400℃에서 N2/H2의 분위기로 30분~60분 동안 열처리시 A, B와 같은 각 웨이퍼(wafer)의 소자 누설전류가 급격히 작아진다.Referring to the present invention with reference to FIGS. 3 and 4, as shown in FIG. 3, when heat treatment is performed for 30 minutes in an atmosphere of N 2 HN 2 at 400 ° C. to 450 ° C., as in B, the heat treatment is not performed. It can be seen that the junction leakage current of the cell is much smaller when the heat treatment is carried out, and each wafer such as A and B is subjected to heat treatment for 30 to 60 minutes in an atmosphere of N 2 / H 2 at 400 ° C. as shown in FIG. The device leakage current of wafers is drastically small.
이상에서 설명한 바와같이 본 발명은 노드(7)를 형성한 후 N2/H2의 포밍가스 분위기에서 400℃~450℃의 온도로 30~60분 동안 열처리하므로써 노드 접합면의 누설전류가 억제되는 효과가 있다.As described above, in the present invention, after forming the node 7, the leakage current at the node junction surface is suppressed by heat treatment at a temperature of 400 ° C. to 450 ° C. for 30 to 60 minutes in a forming gas atmosphere of N 2 / H 2 . It works.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920021019A KR960011647B1 (en) | 1992-11-10 | 1992-11-10 | Dram manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920021019A KR960011647B1 (en) | 1992-11-10 | 1992-11-10 | Dram manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940012623A KR940012623A (en) | 1994-06-24 |
| KR960011647B1 true KR960011647B1 (en) | 1996-08-24 |
Family
ID=19342811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920021019A KR960011647B1 (en) | 1992-11-10 | 1992-11-10 | Dram manufacture |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960011647B1 (en) |
-
1992
- 1992-11-10 KR KR1019920021019A patent/KR960011647B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940012623A (en) | 1994-06-24 |
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