KR960009508A - Data Serial / Parallel Converters in Synchronous Transmissions - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a serial / parallel converter for converting three AU3 serial data into parallel data. The first channel serial / parallel converter 41 converts the data into parallel data and retimates it to 6.48 MHz, which is a three-division clock of 19.44 MHz, and outputs 51.84 Mbps serial data of channel 2 at 51,84 MHz. A second channel serial / parallel converter 42 for converting the parallel data of 6.48 Mbps in synchronization with the 8 division clock and then retiming the output to 6.48 MHz, which is a 3 division clock of 19.44 MHz, and outputting the same; Third-channel serial / to convert the 51.84 Mbps serial data of the synchronous clock into an 8 division clock of 51,84 MHz and convert it to 6.48 Mbps parallel data, which is then retimed to 6.48 MHz, which is a three division clock of 19.44 MHz. Parallel conversion unit 43, the first, second, third A multiplexer 44 for outputting 19.44 Mbps of data by selecting 6.48 Mbps of parallel data output from the null serial / parallel converters 41, 42, and 43 for each channel, and outputting from the multiplexer 44 A retiming unit 45 for retiming and outputting 19.44 Mbps of data to a 19.44 MHz clock, and divides the 51,84 MHz clock into eight and divides the clock of 19.44 MHz into three to divide the first, second, and third channels. Input to the serial / parallel converters 41, 42, 43, respectively, and reset the data of the first, second, and third channel serial / parallel converters 41, 42, and 43 when a phase error of each divided clock is generated. A phase comparison and multiplexer controller 46 for outputting a data selection control signal to the multiplexer 44 and converting a frame pulse signal of 51,84 MHz into a frame start signal of 19.44 MHz, and a frame start signal of the phase comparison and multiplexer controller. Can be synchronized to 19.44Mbps of parallel data. The frame pulse aligner 47 generates a frame start signal.

Description

Data Serial / Parallel Converters in Synchronous Transmissions

Since this is an open matter, no full text was included.

4 is a detailed block diagram showing an embodiment of the present invention.

Claims (1)

A first channel serial that converts 51.84 Mbps serial data of channel 1 into 6.48 Mbps parallel data by synchronizing to an 8 division clock of 51.84 MHz, and then retimates and outputs it to 6.48 MHz, which is a three division clock of 19.44 MHz. The parallel conversion unit 41 converts the 51.84 Mbps serial data of the channel 2 into 6.48 Mbps parallel data by synchronizing to the 8 division clock of 51,84 MHz, and then retimes it to 6.48 MHz, which is a three division clock of 19.44 MHz. second channel serial / parallel conversion unit 42 for retiming and outputting, converting 51.84 Mbps serial data of channel 3 into parallel data of 6.48 Mbps by synchronizing to an 8-division clock of 51,84 MHz, and then converting the same to Outputs from the third channel serial / parallel converter 43 and the first, second, and three channel serial / parallel converters 41, 42, and 43 respectively retiming and outputting at 6.48 MHz, which is a three-division clock. Multi-channel which outputs 19.44Mbps data by selecting one 6.48Mbps parallel data for each channel. A retiming unit 45 for retiming the data of 19.44 Mbps output from the multiplexer 44 and the multiplexer 44 by a clock of 19.44 MHz, and divides the clock of 51,84 MHz into eight and divides the clock of 19.44 MHz. Is divided into three and input to the first, second, and third channel serial / parallel converters 41, 42, and 43, respectively, and when the phase error of each divided clock occurs, the first, second, and third channel serial / parallel. A phase comparison and multiplexer controller for resetting data of the converters 41, 42, 43, outputting a data selection control signal to the multiplexer 44, and converting a 51,84 MHz frame pulse signal to a 19.44 MHz frame start signal; 46) a frame pulse alignment unit 47 for generating a frame start signal which can be synchronized to parallel data of 19.44 Mbps using the frame start signal of the phase comparison and multiplexer control unit. Data serial / parallel Exchange device. ※ Note: The disclosure is based on the initial application.