KR960009055A - Multi-layer metal film formation method - Google Patents

Multi-layer metal film formation method Download PDF

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Publication number
KR960009055A
KR960009055A KR1019940019536A KR19940019536A KR960009055A KR 960009055 A KR960009055 A KR 960009055A KR 1019940019536 A KR1019940019536 A KR 1019940019536A KR 19940019536 A KR19940019536 A KR 19940019536A KR 960009055 A KR960009055 A KR 960009055A
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KR
South Korea
Prior art keywords
film
metal film
insulating film
interlayer insulating
forming
Prior art date
Application number
KR1019940019536A
Other languages
Korean (ko)
Other versions
KR0127246B1 (en
Inventor
최국선
최진호
마숙락
장경식
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940019536A priority Critical patent/KR0127246B1/en
Publication of KR960009055A publication Critical patent/KR960009055A/en
Application granted granted Critical
Publication of KR0127246B1 publication Critical patent/KR0127246B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 제조공정 중 금속막(10), 금속층간절연막(20) SOG막(30), 금속층간절연막(40)막이 교대로 반복 적층되는 다층구조 금속막 형성방법에 있어서 상기 금속층간절연막(40)은 규소가 과포화된 산화막인 것을 특징으로 하는 다층구조 금속막 형성방법에 관한 것으로, 층간 절연막으로 규소(Si)가 과포화된 산화막을 사용하여 SOG막의 경화공정시 발생하는 수분, 수소성분 및 공정완료 후 공기중으로 부터 흡수된 수분이 하부층으로 침투하는 것을 방지함으로써 반도체 소자의 소자특성을 향상시키는 효과를 갖는다.The present invention provides a method for forming a multilayer structure metal film in which a metal film 10, an interlayer insulating film 20, an SOG film 30, and an interlayer insulating film 40 are alternately stacked in a semiconductor manufacturing process. 40) relates to a method for forming a multi-layered metal film, characterized in that the silicon is a supersaturated oxide film, wherein water, hydrogen components and processes generated during the curing process of the SOG film using an oxide film supersaturated with silicon (Si) as an interlayer insulating film. After completion, the moisture absorbed from the air is prevented from penetrating into the lower layer, thereby improving the device characteristics of the semiconductor device.

Description

다층구조 금속막 형성방법Multi-layer metal film formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 일실시예에 따라 이중구조 금속막이 형성된 상태를 나타낸 단면도.2 is a cross-sectional view showing a state in which a dual-structure metal film is formed according to an embodiment of the present invention.

Claims (1)

반도체 소자 제조공정 중 금속막, 금속층간절연막, SOG막, 금속층간절연막이 적어도 2회 이상 교대로 반복 적층되는 다층구조 금속막 형성방법에 있어서, 상기 금속층간절연막은 규소가 과포화된 산학막인 것을 특징으로 하는 다층구조 금속막 형성방법.In the method of forming a multilayer structure metal film in which a metal film, an intermetallic insulating film, an SOG film, and an intermetallic insulating film are alternately repeatedly stacked at least two or more times during a semiconductor device manufacturing process, the interlayer insulating film is an amorphous supersaturated silicon film. A method of forming a multi-layer metal film, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940019536A 1994-08-08 1994-08-08 Forming method for insulating film between layers of semiconductor device KR0127246B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940019536A KR0127246B1 (en) 1994-08-08 1994-08-08 Forming method for insulating film between layers of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940019536A KR0127246B1 (en) 1994-08-08 1994-08-08 Forming method for insulating film between layers of semiconductor device

Publications (2)

Publication Number Publication Date
KR960009055A true KR960009055A (en) 1996-03-22
KR0127246B1 KR0127246B1 (en) 1997-12-29

Family

ID=19389999

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940019536A KR0127246B1 (en) 1994-08-08 1994-08-08 Forming method for insulating film between layers of semiconductor device

Country Status (1)

Country Link
KR (1) KR0127246B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990081277A (en) * 1998-04-28 1999-11-15 윤종용 Stress control method of insulating film
US8584578B2 (en) 2006-09-07 2013-11-19 Bravilor Holding B.V. Preparing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990081277A (en) * 1998-04-28 1999-11-15 윤종용 Stress control method of insulating film
US8584578B2 (en) 2006-09-07 2013-11-19 Bravilor Holding B.V. Preparing device

Also Published As

Publication number Publication date
KR0127246B1 (en) 1997-12-29

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