KR930001396A - Metal wire manufacturing method - Google Patents

Metal wire manufacturing method Download PDF

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Publication number
KR930001396A
KR930001396A KR1019910010069A KR910010069A KR930001396A KR 930001396 A KR930001396 A KR 930001396A KR 1019910010069 A KR1019910010069 A KR 1019910010069A KR 910010069 A KR910010069 A KR 910010069A KR 930001396 A KR930001396 A KR 930001396A
Authority
KR
South Korea
Prior art keywords
opening
substrate
glass substrate
photoresist pattern
metal wire
Prior art date
Application number
KR1019910010069A
Other languages
Korean (ko)
Inventor
배병성
배용국
김남덕
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910010069A priority Critical patent/KR930001396A/en
Priority to JP4070544A priority patent/JPH05107553A/en
Publication of KR930001396A publication Critical patent/KR930001396A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames

Abstract

내용 없음No content

Description

금속 배선 제조 방법Metal wire manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 이 발명에 따른 일실시예를 나타내는 금속배선 제조공정도이다.2 is a manufacturing process diagram of a metal wire showing an embodiment according to the present invention.

Claims (4)

반도체 장치의 제조방법에 있어서, 유리기판의 상부에 포토레지스트 패턴을 형성하는 제1공정과, 상기 포토레지스트 패턴을 통해 노출된 유리기판을 소정두께 제거하여 개구부를 형성하는 제2공정과, 상기 구조의 전 표면에 금속막을 도포하여 유리기판의 개구부를 메꾸는 제3공정과, 상기 구조의 개구부를 제외한 부분의 금속막과 포토레지스트 패턴을 제거하는 제4공정으로 이루어지는 것을 특징으로 하는 금속배선 제조방법.A method of manufacturing a semiconductor device, comprising: a first step of forming a photoresist pattern on an upper portion of a glass substrate; a second step of forming an opening by removing a predetermined thickness of the glass substrate exposed through the photoresist pattern; and the structure And a fourth step of filling the opening of the glass substrate by applying a metal film to the entire surface of the substrate, and a fourth step of removing the metal film and the photoresist pattern in the portions except the opening of the structure. . 제1항에 있어서, 상기 제1공정에 있어서 SiO2, Si3N4등 절연막을 기판으로 사용하는 것을 특징으로 하는 금속배선 제조방법.The method of claim 1, wherein in the first step, an insulating film such as SiO 2 , Si 3 N 4, or the like is used as the substrate. 제1항에 있어서, 상기 제1공정에 있어서, BPSG, USG, PSG, 유리기판 등의 유리재질의 절연물질을 기판으로 사용하는 것을 특징으로하는 금속배선 제조방법.The method of claim 1, wherein in the first step, a glass insulating material such as BPSG, USG, PSG, and glass substrate is used as the substrate. 제1항에 있어서, 상기 제2공정에 있어서 습식에칭 또는 건식에칭 중 어느 한가지 방법에 의하여 상기 개구부를 형성하는 것을 특징으로 하는 금속배선 제조방법.The method of claim 1, wherein the opening is formed by any one of wet etching and dry etching in the second step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910010069A 1991-06-18 1991-06-18 Metal wire manufacturing method KR930001396A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910010069A KR930001396A (en) 1991-06-18 1991-06-18 Metal wire manufacturing method
JP4070544A JPH05107553A (en) 1991-06-18 1992-03-27 Manufacture of metallic wiring of active matrix lcd

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910010069A KR930001396A (en) 1991-06-18 1991-06-18 Metal wire manufacturing method

Publications (1)

Publication Number Publication Date
KR930001396A true KR930001396A (en) 1993-01-16

Family

ID=19315948

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910010069A KR930001396A (en) 1991-06-18 1991-06-18 Metal wire manufacturing method

Country Status (2)

Country Link
JP (1) JPH05107553A (en)
KR (1) KR930001396A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937465B2 (en) 2002-01-31 2005-08-30 Samsung Electronics Co., Ltd. Portable computer having a latch apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010046141A (en) 1999-11-10 2001-06-05 구본준 Method for forming a signal line and TFT using the method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63235983A (en) * 1987-03-24 1988-09-30 富士通株式会社 Manufacture of thin film transistor panel
JPH04170519A (en) * 1990-11-01 1992-06-18 Matsushita Electric Ind Co Ltd Wiring for plane display and forming method thereof and nonlinear resistance element for liquid crystal display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937465B2 (en) 2002-01-31 2005-08-30 Samsung Electronics Co., Ltd. Portable computer having a latch apparatus

Also Published As

Publication number Publication date
JPH05107553A (en) 1993-04-30

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