KR960008310B1 - Method of making a stacked capacitor - Google Patents
Method of making a stacked capacitor Download PDFInfo
- Publication number
- KR960008310B1 KR960008310B1 KR1019930011067A KR930011067A KR960008310B1 KR 960008310 B1 KR960008310 B1 KR 960008310B1 KR 1019930011067 A KR1019930011067 A KR 1019930011067A KR 930011067 A KR930011067 A KR 930011067A KR 960008310 B1 KR960008310 B1 KR 960008310B1
- Authority
- KR
- South Korea
- Prior art keywords
- polycrystalline silicon
- forming
- silicon layer
- insulating oxide
- oxide film
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 238000003860 storage Methods 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도 내지 제6도는 본 발명에 의해 스택캐패시터를 제조하는 단계를 도시한 단면도.1 through 6 are cross-sectional views illustrating steps of manufacturing a stack capacitor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 소자분리 산화막1: silicon substrate 2: device isolation oxide film
3 : 제1절연산화막 4 : 도전배선3: first insulating oxide film 4: conductive wiring
5 : 제2절연산화막 6 : 제3절연산화막5: second insulating oxide film 6: third insulating oxide film
7 : 제1다결정 실리콘층 8 : 제4절연산화막7: first polycrystalline silicon layer 8: fourth insulating oxide film
9 : 제2다결정 실리콘층 10A : 제2다결정 실리콘 스페이서9: second polycrystalline silicon layer 10A: second polycrystalline silicon spacer
11 : 제3다결정 실리콘층 20 : 저장전극11: third polycrystalline silicon layer 20: storage electrode
22 : 캐패시터 유전체막 24 : 플레이트 전극22 capacitor dielectric film 24 plate electrode
본 발명은 반도체 소자의 스태캐패시터 제조방법에 관한 것으로, 특히 캐패시터 콘택홀 형성을 위한 마스크공정을 실시하되, 저장전극의 패턴을 형성하는 저장전극 마스크공정은 생략하여 캐패시터 제조공정을 단순화하고, 캐패시터 콘택홀을 준자기정렬(Quasi-Selfalign)로 형성하여 미스얼라인이나 이웃하는 도전배선간의 단락발생에 대하여 공정여유도를 더 확보할 수 있는 스택캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, a mask process for forming a capacitor contact hole is performed, but a storage electrode mask process for forming a pattern of a storage electrode is omitted, thereby simplifying a capacitor manufacturing process and a capacitor contact. The present invention relates to a method of manufacturing a stack capacitor, in which holes are formed by quasi-selfalignment to further secure process margins against occurrence of short circuits between misaligned or neighboring conductive wirings.
캐패시터 콘택을 실리콘기판의 활성층에 직접적으로 형성하게 되면 캐패시터 콘택과 이웃하는 도전체와 단락발생 확률이 높게 된다. 또한 캐패시터 제조시, 콘택마스크 및 저장전극 마스크 공정을 거치게 되면 공정이 복잡해지고 콘택홀과 캐패시터와 미스얼라인 발생하게 되어 반도체 소자의 신뢰도가 낮아질 수 밖에 없다.If the capacitor contact is directly formed on the active layer of the silicon substrate, the probability of occurrence of a short circuit with a conductor contact and a neighboring conductor becomes high. In addition, when the capacitor is manufactured, the contact mask and the storage electrode mask process are complicated, and the contact hole, the capacitor and the misalignment are generated, thereby reducing the reliability of the semiconductor device.
따라서, 본 발명은 콘택홀 마스크를 사용해서 절연층의 일정두께가 식각된 홈을 형성하고, 홈 측벽에 도전층 스페이서를 형성하고 이 도전층 스페이서를 마스크로 하여 콘택홀을 형성함으로써 콘택홀 형성시 미스얼라인에 대한 공정여유도를 확보하고, 상기 도전층 스페이서를 저장전극으로 이용하여 저장전극 마스크 공정이 없이 스택캐패시터 제조방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, a contact hole mask is used to form a groove in which a predetermined thickness of the insulating layer is etched, a conductive layer spacer is formed on the sidewall of the groove, and a contact hole is formed using the conductive layer spacer as a mask. It is an object of the present invention to provide a method of manufacturing a stack capacitor without securing a process margin for misalignment and using the conductive layer spacer as a storage electrode without a storage electrode mask process.
이하, 첨부한 도면을 참고하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제6도는 본 발명에 의해 스택캐패시터를 제조하는 단계를 도시한 단면도이다.1 to 6 are cross-sectional views showing the steps of manufacturing a stack capacitor according to the present invention.
제1도는 실리콘기판(1) 상부에 소자분리 산화막(2)을 형성하고, 그 상부에 워드라인(도시안됨)을 형성한 후, 전체구조 상부에 제1절연산화막(3)을 평탄하게 형성하고, 도전배선(4) 예를 들어 비트라인을 형성하고, 그 상부에 제2절연산화막(5), 평탄화용 제3절연산화막(6), 제1다결정 실리콘층(7), 제4절연사화막(8)을 각각 예정된 두께로 적층한 다음, 콘택마스크(도시안됨)를 이용한 식각공정으로 제4절연산화막(8)을 식각하여 제1다결정 실리콘층(7)이 노출된 홈을 형성하고, 전체적으로 제2다결정 실리콘층(10)을 증착한 단면도이다. 여기서 제4절연산화막(8)은 캐패시터의 저장전극의 높이를 고려한 두께로 형성해야 한다.In FIG. 1, the device isolation oxide film 2 is formed on the silicon substrate 1, the word line (not shown) is formed on the silicon substrate 1, and then the first insulating oxide film 3 is formed flat on the entire structure. For example, a bit line, and a second insulating oxide film 5, a planarization third insulating oxide film 6, a first polycrystalline silicon layer 7, and a fourth insulating still film (8) is laminated to a predetermined thickness, and the fourth insulating oxide film 8 is etched by an etching process using a contact mask (not shown) to form grooves in which the first polycrystalline silicon layer 7 is exposed. A cross-sectional view of depositing the second polycrystalline silicon layer 10. In this case, the fourth insulating oxide film 8 should be formed to have a thickness in consideration of the height of the storage electrode of the capacitor.
제2도는 제1도 공정후 상기 제2다결정 실리콘층(10)과 홈에 있는 제1다결정 실리콘층(7)을 블랭킷 건식식각(Blanket Dry Etch)하여 홈 측벽에 제2다결정 실리콘 스페이서(10A)를 형성한 단면도로서, 제2다결정 실리콘 스페이스(10A)의 두께(A)만큼 후에 형성된 콘택홀과 도전배선(4)의 미스얼라인에 대한 공정여유를 확보해준다.FIG. 2 illustrates a blanket dry etching process of the second polycrystalline silicon layer 10 and the first polycrystalline silicon layer 7 in the groove after the FIG. 1 process to form a second polycrystalline silicon spacer 10A on the sidewall of the groove. Is a cross-sectional view of the second polycrystalline silicon space (10A) to ensure the process margin for the misalignment of the contact hole and the conductive wiring (4) formed later by the thickness (A).
제3도는 제2도 공정후 제2다결정 실리콘 스페이서(10A)와 제1다결정 실리콘층(7)을 마스크로하여 홈 저부에 있는 제3절연산화막(6), 제2절연산화막(5), 제1절연산화막(3)을 순차적으로 건식식각하여 실리콘기판(1)이 노출된 미세콘택홀(13)을 형성한 단면도로서, 콘택홀(13) 상부에는 제2다결정 실리콘 스페이서(10A)가 형성되고, 하부절연 산화막들이 건식식각되는 동안에 제4절연산화막(8)이 동시에 식각되어 제거된다.FIG. 3 shows the third insulating oxide film 6, the second insulating oxide film 5, and the third insulating oxide film at the bottom of the groove after the process of FIG. 2 using the second polycrystalline silicon spacer 10A and the first polycrystalline silicon layer 7 as a mask. 1 is a cross-sectional view of a micro contact hole 13 in which the silicon substrate 1 is exposed by dry etching the insulating oxide film 3 sequentially. A second polycrystalline silicon spacer 10A is formed on the contact hole 13. The fourth insulating oxide film 8 is simultaneously etched and removed while the lower insulating oxide films are dry etched.
제4도는 제3도 공정후, 전체적으로 제3다결정 실리콘층(11)을 증착하여 콘택홀(13)에 채우고, 콘택홀(13)상부에는 돌출부가 형성됨을 도시한 단면도이다.4 is a cross-sectional view showing that after the process of FIG. 3, the third polycrystalline silicon layer 11 is deposited and filled in the contact hole 13, and a protrusion is formed on the contact hole 13.
제4도는 제4도 공정후, 상기 제3다결정 실리콘층(11), 제2다결정 실리콘 스페이서(10A)와 제1다결정 실리콘층(7)을 블랭킷 건식식각하되 제3절연산화막(6)이 노출되기까지 식각하여 실리콘기판(1)에 콘택된 독립적인 저장전극(20)을 형성한 단면도이다.FIG. 4 is a blanket dry etching of the third polycrystalline silicon layer 11, the second polycrystalline silicon spacer 10A and the first polycrystalline silicon layer 7 after the process of FIG. 4, but the third insulating oxide layer 6 is exposed. FIG. 1 is a cross-sectional view of an independent storage electrode 20 contacted to the silicon substrate 1 by etching.
제5도는 제4도 공정후, 상기 제3다결정 실리콘층(11), 제2다결정 실리콘 스페이서(10A)와 제1다결정 실리콘층(7)을 블랭킷 건식식각하되 제3절연산화막(6)이 노출되기까지 식가하여 실리콘기판(1)에 콘택된 독립적인 저장전극(20)을 형성한 단면도이다.FIG. 5 is a blanket dry etching of the third polycrystalline silicon layer 11, the second polycrystalline silicon spacer 10A, and the first polycrystalline silicon layer 7 after the process of FIG. 4, but the third insulating oxide layer 6 is exposed. It is sectional drawing which formed the independent storage electrode 20 contacted to the silicon substrate 1 by cooling until it has become.
제6도는 제5도 공정후, 저장전극(20) 표면에 캐패시터 유전체막(22)과 플레이트전극(24)을 형성한 단면도이다.FIG. 6 is a cross-sectional view of the capacitor dielectric film 22 and the plate electrode 24 formed on the storage electrode 20 after the process of FIG. 5.
상기한 본 발명에 의하면 캐패시터 저장전극 패턴을 형성하기 위한 마스크공정을 생략할 수 있음으로 인하여 공정의 단순화에 기여하여 반도체 소자의 수율을 향상시킬 수 있다.According to the present invention described above, since the mask process for forming the capacitor storage electrode pattern can be omitted, the yield of the semiconductor device can be improved by contributing to the simplification of the process.
또한, 다결정 실리콘 스페이서를 콘택홀 형성시 마스크로 사용함으로써 콘택홀의 미스얼라인에 대한 공정여유도를 더 확보할 수 있다.In addition, by using the polycrystalline silicon spacer as a mask in forming the contact hole, it is possible to further secure the process margin with respect to the misalignment of the contact hole.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930011067A KR960008310B1 (en) | 1993-06-17 | 1993-06-17 | Method of making a stacked capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930011067A KR960008310B1 (en) | 1993-06-17 | 1993-06-17 | Method of making a stacked capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950002026A KR950002026A (en) | 1995-01-04 |
| KR960008310B1 true KR960008310B1 (en) | 1996-06-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930011067A KR960008310B1 (en) | 1993-06-17 | 1993-06-17 | Method of making a stacked capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960008310B1 (en) |
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1993
- 1993-06-17 KR KR1019930011067A patent/KR960008310B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR950002026A (en) | 1995-01-04 |
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