KR960008055B1 - Frequency multiplying circuit for multi-sync. projector system - Google Patents

Abstract

The circuit generates a rectifier signal with a vertical synchronization signal in order to display a certain size of the cross hatched pattern on the screen without any relation to the input picture signal mode. The circuit includes an edge detector, a horizontal counter, a divider, a latch, a period counter, a comparator, and a two-step divider. It prevents an influence due to the display information loss along with an insensibility to the graphic size variation.

Description

Frequency multiplier circuit in multi-sync projector system

1 is a frequency multiplier circuit diagram of a multi-sync projector system according to the present invention.

2 and 3 (a), (b) is a waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

10: edge detection unit 20: horizontal counter

30: divider 40: latch

50: cycle counter 60: 2 minute cycle

OR1: Oagate COMP1: Comparator

a: Horizontal sync signal input b: Clock signal input

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing system using a multi-sync projector. More particularly, the present invention relates to horizontal synchro in order to display a cross hatch pattern having a constant size regardless of a mode of an input video signal. A frequency multiplication circuit of a multi-sync projector system for generating a reference signal using a signal.

In particular, the present invention relates to a frequency multiplying circuit of a digital convergence device of a display device such as a CRT projector and a projection TV that accommodates multiple synchronization, and has a constant number regardless of the horizontal and vertical frequencies of an input video signal. The present invention relates to a frequency multiplication circuit of a digital convergence device in a multi-sync projector system for generating a predetermined reference signal for displaying a cross hatch pattern having a grid.

In general, when processing an image signal corresponding to multi-sync in an image processing system using a multi-key sync projector, the horizontal frequency as a reference when dividing the screen by the input image signal into a fixed number of columns is used for each mode of the input image signal. Depends on each other. For example, 21.5kHz for EGA (Enhanced Graphic Adapter), 15.75kHz for NTSC (National Television System Committee), etc., each horizontal frequency is different for VGA (Video Graphic Adapter) and CGA (Color Graphic Adapter). When the video signal input for a certain time is displayed on the screen, the screen size displayed on the screen is different according to each mode.

In general, convergence refers to a display having three electron guns, in which R, G, and B three electron beams are focused on a shadow mask. That is, since the positions of the R, G, and B electron guns are different, and the distance from the deflection center point to the shadow mask surface or the fluorescent surface is different depending on the position on the shadow mask surface or the fluorescent surface, adjacent phosphors do not emit light and do not become false colors. Adjust the convergence to prevent the color from falling out.

In general, a multi-synchronous display device of an image processing system using a multi-sync projector includes a screen adjustment circuit called digital convergence, and a checkerboard cross generated inside the digital convergence circuit. The convergence is corrected so that the hatch pattern (CROSS HATCH PATTERN) matches the grid displayed on the screen by the red, green, and blue (R, G, B) electron guns.

The digital convergence according to the prior art has a large number of cross hatch pattern grids as the scanning speed of the cross hatch pattern stored in the pattern memory is increased in the case of a signal having a high horizontal frequency, and in contrast, in the case of a signal having a low horizontal frequency, a pattern memory is used. As the scanning speed of the cross hatch pattern stored in the device becomes slow, a small number of cross hatch pattern lattice appears. That is, the size and number of cross-hatch pattern grids displayed on the screen vary according to the horizontal and vertical synchronization frequencies of the input video signal (depending on the mode of the input signal). Accordingly, the size and number of the cross hatch patterns displayed on the screen screen fixed to a fixed size (N * N) are inconsistent depending on the mode of the input image signal, so that an additional circuit is required.

Hereinafter, for convenience of explanation, for convenience of explanation, the video signals input to the digital convergence device are referred to as A, B, and C signals according to the horizontal frequency, and A, B, The period of the horizontal synchronous signal of the C signal will be described as 10 seconds, 7 seconds, and 5 seconds, respectively.

When the horizontal synchronization signal as a reference for the digital convergence device is divided into 10 seconds, each signal named A, B, and C signals is divided vertically into an absolute time interval of 1 second.

Since the period of the horizontal synchronization signal of the A signal is a 10-second period, dividing the A signal into 1-second periods results in 10 sections. The period of the horizontal synchronous signal of the C signal is a 5 second interval, so when the C signal is divided into 1 second intervals, the interval is 5 sections. Therefore, the A signal can display all the grids of the cross hatch pattern in 10 sections, but the B signal and the C signal cannot display all the grids of the cross hatch pattern. That is, the screen size of the cross hatch pattern displayed on the screen is different depending on the mode of the input video signal.

Also, if you want to make 10 sections vertically for any signal A, B, or C (that is, if you want to make the screen size of the displayed cross hatch pattern the same), the A signal will display all information amount in 10 sections at 1 second intervals. Although it can be displayed, since the B signal is displayed at the interval of 0.7 seconds and the C signal is displayed at the 10 intervals at 0.5 second intervals, there is a disadvantage that all the information can not be displayed.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to generate a signal that is a multiplied number of the signal based on a horizontal synchronization signal corresponding to a multi-sync, and to fix one screen for the multi-sync. When divided by the number, it is intended to provide a frequency multiplication circuit that does not feel a change in screen size for each sink and prevents loss of display information.

In order to achieve the above object, the frequency multiplication circuit of the multi-sync projector system according to the present invention comprises: horizontal synchronous detection means for receiving a horizontal synchronous signal and a clock signal to detect a down edge of the horizontal synchronous signal; A horizontal counter that counts a clock signal and is cleared according to the output of the horizontal synchronous detection means; First dispensing means for dividing the output of the horizontal counter; A counter that counts a clock signal and is cleared when the counted value is the same as the output of the first division means or when the horizontal synchronous signal is input; And comparing means for comparing the output of the first dispensing means with the output of the periodic counter; It is preferable to include a second dispensing means for dividing the output of the comparing means. Further, in the frequency multiplication circuit of the above-described multi-sync projector system, it is preferable to further include latch means for delaying the output of the first division means for one horizontal period. Here, the counter preferably includes an OR of the horizontal synchronizing signal and the output of the comparator, and a cycle count that counts a clock signal and is cleared according to the output of the OR gate. It is preferable to divide the output of the horizontal counter according to the mode of the video signal.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1 is a diagram illustrating a frequency multiplication circuit of a multi-sync projector system according to the present invention. The configuration and operation of FIG. 1 are briefly described as follows.

First, the horizontal sync signal H-Sync input terminal a and the clock signal CLK input terminal b are connected to the input terminal of the edge detector 10 to detect the down edge of the input horizontal sync signal.

Then, the output terminal of the edge detector 10 is connected to the input clear terminal of the horizontal counter 20 and the floc signal input terminal b is connected to the clock terminal of the horizontal counter 20 while one horizontal line of the video signal is input. The clock signal is counted, and the horizontal counter 20 is cleared according to the output of the edge detector 10.

The output terminal of the horizontal counter 20 is connected to the input terminal of the divider 30 and divided by a predetermined number of known numbers to obtain a desired multiplication frequency from the output of the horizontal counter 20. In addition, the output terminal of the divider 30 is connected to the input terminal of the latch 40 to maintain the output of the divider 30 for the next one horizontal line, and the output terminal of the latch 40 is held on one side of the comparator COMP1. To.

On the other hand, the clock signal input terminal (b) is connected to the clock terminal of the periodic counter 50, and the clear gate of the periodic counter 50 has an OR gate OR1 that logically calculates the horizontal synchronization signal and the output of the comparator COMP1. When the clock signal is counted and the horizontal synchronous signal is input or the output of the periodic counter 50 is the same as the output of the latch 50, the clock signal is cleared.

The output terminal of the latch 40 is connected to one input terminal of the comparator COMP1, the output terminal of the cycle counter 50 is connected to the other input terminal of the comparator COMP1, and the output terminal of the comparator COMP1 is a 50% duty signal. It is connected to the input terminal of the two divider 60 to make a desired reference signal.

Hereinafter, the present invention will be described in more detail with reference to FIGS. 1 to 3.

The edge detector 10 detects the down edge of the first horizontal synchronous signal inputted as in the H-DOWN waveform of FIG. In accordance with this detection output, the horizontal counter 20 counts the clock signal while one horizontal line of the video signal is input.

3 (a) is the frequency waveform during the first horizontal line, and the peripheral waveform diagram of the second horizontal synchronous signal generated after counting all the first horizontal lines in the horizontal counter 20 and the peripheral waveform diagram of the second horizontal line. Is the same as (b) of FIG. 2 and FIG.

When all the lines are counted in the horizontal counter 20, this counting value is inputted to the divider 30 and divided into a predetermined number so as to obtain a desired multiplication frequency, and then inputted to the latch 40 for the next horizontal line. maintain. Here, the divider 30 divides the output of the horizontal counter 20 according to the mode of the input image signal.

The period counter 50 receives and counts a clock signal and is cleared according to the output of the OR gate OR1. That is, the OR gate OR1 inputs the horizontal synchronization signal H-Sync by inputting the horizontal synchronization signal H-Sync and the output signal of the comparator COMP1 to the clear terminal of the periodic counter 50, or When the value output from the cycle counter 50 becomes equal to the value stored in the latch 40, the cycle counter 50 is cleared. This relational waveform is shown in DIVA, CNT2, and EQUAL in FIG.

Here, the cycle counter 50 repeats the counting periodically for each horizontal line to form a periodic waveform, which is shown in CNT2 and EQUAL of FIG. 3 (b). In addition, one input terminal of the OR gate OR1 may be connected to the output terminal of the edge detector 10, and the other input terminal of the OR gate OR1 may be connected to the output terminal of the comparator COMP1. (Not shown)

On the other hand, the comparator COMP1 checks whether the output of the cycle counter 50 and the output of the latch 40 are the same and sends out the comparison output EQUAL. The comparison output of the comparator COMP1 has a multiplication frequency of 50% duty. In order to obtain this, the frequency divider is divided into two frequency dividers 60 to obtain the final output waveform. That is, it is generated as a clock signal having a duty of 50% multiplied by a desired value with respect to the horizontal synchronization signal.

Therefore, this signal can be used as a reference signal when one screen is divided into a fixed number of columns for the multi-sync of the video signal by varying the multiplication frequency in each use mode, and the signal is output at the 50% duty. This is because 50% duty signal is used. Here, the number of jets of the divider 40 may vary according to the mode of the input image signal.

As described above, the present invention generates a signal that is a multiplication of any number of signals based on the multi-sync horizontal synchronization signal, so that when one screen is divided by a fixed number of columns for the multi-sync, The change is not felt and there is an effect of preventing the loss of display information.

Claims (5)

Horizontal synchronous detection means for receiving a horizontal synchronous signal and a clock signal and detecting a down edge of the horizontal synchronous signal; A horizontal counter that counts the clock signal and is cleared according to the output of the horizontal synchronous detection means; First dispensing means for dispensing the output of the horizontal counter; A counter that counts the clock signal and is cleared when the counted value is equal to the output of the first division means or when the horizontal synchronization signal is input; Comparison means for comparing an output of the first dispensing means and an output of the periodic counter; And second dividing means for dividing the output of the comparing means. 2. The frequency multiplier circuit of claim 1, further comprising latching means for delaying the output of said first dividing means for one horizontal period. 2. The frequency multiplier circuit of claim 1, wherein the first division means divides the output of the horizontal counter according to a mode of an input video signal. The multi-sync according to claim 1, wherein the counter comprises an orifice for performing an OR operation on a horizontal synchronization signal and an output of a comparator, and a cycle count that counts the clock signal and is cleared according to the output of the oragate. Frequency multiplication circuit of the projector system. The method of claim 1, further comprising: an orifice for counting the clock signal and performing an OR operation on the output of the detection means and the output of the comparator, and a periodic counter that counts the clock signal and is cleared according to the output of the oragate. A frequency multiplier circuit of a multi-sync projector system.