KR930015746A - Frequency multiplication circuit - Google Patents

Frequency multiplication circuit Download PDF

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Publication number
KR930015746A
KR930015746A KR1019910024388A KR910024388A KR930015746A KR 930015746 A KR930015746 A KR 930015746A KR 1019910024388 A KR1019910024388 A KR 1019910024388A KR 910024388 A KR910024388 A KR 910024388A KR 930015746 A KR930015746 A KR 930015746A
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KR
South Korea
Prior art keywords
horizontal
counter
output
latch
input terminal
Prior art date
Application number
KR1019910024388A
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Korean (ko)
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KR960008055B1 (en
Inventor
유경질
Original Assignee
강진구
삼성전자 주식회사
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Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019910024388A priority Critical patent/KR960008055B1/en
Publication of KR930015746A publication Critical patent/KR930015746A/en
Application granted granted Critical
Publication of KR960008055B1 publication Critical patent/KR960008055B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Synchronizing For Television (AREA)

Abstract

이 발명은 멀티싱크에 대응한 영상신호처리에 관한 것으로, 에지검출기(10)에서 수평동기신호의 에지를 검출하고 수평카운터(20) 및 주기카운터(50)에서 1수평신호구간을 카운팅하며 제산기(30)에서 상기 수평카운터(20)의 출력을 원하는 체배주파수를 얻기위해 설정된 수로 분주시켜 래치(40)에 유지시키고, 비교기(COMP1)에서 래치(40)로부터의 신호와 주기카운터(50)로부터의 신호를 비교한 후 이 비교 출력을 2분 주기(60)에서 2분주시켜 50% 듀티의 신호를 얻어 이 신호를 영상신호의 멀티싱크에 대해 한 화면을 고정된 컬럼수로 나눌때 기준이 되는 신호로 사용할 수 있게 한 것이다.The present invention relates to image signal processing corresponding to multi-sync, wherein the edge detector 10 detects the edge of the horizontal synchronization signal and counts one horizontal signal section in the horizontal counter 20 and the periodic counter 50 and divides the divider. At 30, the output of the horizontal counter 20 is divided into a set number to obtain a desired multiplication frequency, and held in the latch 40, and the signal from the latch 40 and the periodic counter 50 at the comparator COMP1. After comparing these signals, divide the output of this comparison by 2 minutes at 60 minutes to get 50% duty signal, which is used as a reference when dividing a screen by a fixed number of columns for multi-sync of video signals. It can be used as a signal.

Description

주파수 체배회로Frequency multiplication circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 이 발명에 따른 주파수 체배회로도, 제2도는 제1도 각부의 파형도이다.1 is a frequency multiplier circuit diagram according to the present invention, and FIG. 2 is a waveform diagram of each part of FIG.

Claims (1)

수평동기신호 입력단(a) 및 클럭신호입력단(b)에 연결되어 입력되는 수평동기신호의 다운에지를 검출하는 에지검출기(10)와, 상기 에지검출기(10) 및 클럭신호 입력단(b)에 연결되어 상기 에지검출기(10)의 검출출력에 따라 수평라인을 카운팅하는 수평카운터(20)와, 상기 수평카운터(20)에 연결되어 상기 수평카운터(20) 출력을 원하는 체배주파수를 얻기위해 설정된 수로 나누는 나눗셈기(30)와, 상기 나눗셈기(30)에 연결되어 나눗셈기(30)의 출력을 일정시간 유지하는 래치(40)와, 일측입력단이 상기 수평동기신호 입력단(a)에 연결되어 입력되는 신호를 논리합하는 오아게이트(OR1)와, 상기 클럭신호 입력단(b) 및 오아게이트(OR1)에 연결되어 수평동기신호의 시작부터 카운팅을 시작해 카운팅값이 상기 래치(40)에 저장된 값과 동일한 값이 되면 클리어되는 주기카운터(50)와, 상기 래치(40) 및 주기카운터(50)에 연결되어 상기 래치(40) 및 주기카운터(50)의 출력을 비교하며, 상기 오아게이트(OR1)의 타측입력을 제공하는 비교기(COMP1)와, 상기 비교기(COMP1)에 연결되어 상기 비교기(COMP1) 출력을 50% 듀티의 신호로 만드는 2분주기(60)와, 로 구성되는 주파수 체배회로.An edge detector 10 connected to a horizontal synchronous signal input terminal (a) and a clock signal input terminal (b) for detecting a down edge of an input horizontal synchronous signal, and connected to the edge detector 10 and a clock signal input terminal (b) And a horizontal counter 20 for counting a horizontal line according to the detection output of the edge detector 10 and a horizontal counter 20 connected to the horizontal counter 20 to divide the horizontal counter 20 output into a set number to obtain a desired multiplication frequency. A divider 30, a latch 40 connected to the divider 30 to maintain the output of the divider 30 for a predetermined time, and one input terminal connected to the horizontal synchronous signal input terminal a It is connected to the OR gate OR1 for ORing the signal, the clock signal input terminal b, and the OR gate OR1 to start counting from the start of the horizontal synchronization signal, and the counting value is the same as the value stored in the latch 40. Cleared when Comparator connected to the counter 50, the latch 40 and the cycle counter 50 to compare the output of the latch 40 and the cycle counter 50, and provides the other input of the OR gate OR1 And a divider (60) connected to the comparator (COMP1) and making the output of the comparator (COMP1) a signal of 50% duty. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910024388A 1991-12-26 1991-12-26 Frequency multiplier circuit in multi-sync projector system KR960008055B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910024388A KR960008055B1 (en) 1991-12-26 1991-12-26 Frequency multiplier circuit in multi-sync projector system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910024388A KR960008055B1 (en) 1991-12-26 1991-12-26 Frequency multiplier circuit in multi-sync projector system

Publications (2)

Publication Number Publication Date
KR930015746A true KR930015746A (en) 1993-07-24
KR960008055B1 KR960008055B1 (en) 1996-06-19

Family

ID=19326029

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910024388A KR960008055B1 (en) 1991-12-26 1991-12-26 Frequency multiplier circuit in multi-sync projector system

Country Status (1)

Country Link
KR (1) KR960008055B1 (en)

Also Published As

Publication number Publication date
KR960008055B1 (en) 1996-06-19

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