KR960006700B1 - Manufacturing method of poly silicon gate electrode - Google Patents
Manufacturing method of poly silicon gate electrode Download PDFInfo
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- KR960006700B1 KR960006700B1 KR1019930004038A KR930004038A KR960006700B1 KR 960006700 B1 KR960006700 B1 KR 960006700B1 KR 1019930004038 A KR1019930004038 A KR 1019930004038A KR 930004038 A KR930004038 A KR 930004038A KR 960006700 B1 KR960006700 B1 KR 960006700B1
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- polysilicon
- oxide film
- gate electrode
- dry etching
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 61
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 3
- 238000001312 dry etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000866 electrolytic etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 229910001392 phosphorus oxide Inorganic materials 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- VSAISIQCTGDGPU-UHFFFAOYSA-N tetraphosphorus hexaoxide Chemical compound O1P(O2)OP3OP1OP2O3 VSAISIQCTGDGPU-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 폴리실리콘 게이트 전극 제조방법에 관한 것이다. 특히 고집적 반도체 소자 제조에 적합하도록 게이트 전극 형성시 폴리실리콘막 위에 산소를 이용하여 얇은 산화막을 성장시켜서 후공정의 스캡 카브리지를 개선한 폴리실리콘 게이트 전극 제조방법에 관한 것이다.The present invention relates to a polysilicon gate electrode manufacturing method. In particular, the present invention relates to a polysilicon gate electrode manufacturing method of improving a cap bridge in a later process by growing a thin oxide film using oxygen on a polysilicon layer to form a gate electrode suitable for manufacturing a highly integrated semiconductor device.
종래기술은 제1도(가)에 도시된 바와같이, 실리콘 기잔(1)위에 게이트산화막(2)을 형성하고 그위에 폴리실리콘(3)을 증착한 후 POCL3개스를 이용해서 폴리실리콘에 P이온을 도핑(DOPING)시켜서 폴리실리콘층이 도전성을 띄게 한다.In the prior art, as shown in FIG. 1A, a gate oxide film 2 is formed on a silicon base 1, polysilicon 3 is deposited thereon, and then P is deposited on polysilicon using POCL 3 gas. The polysilicon layer is made conductive by doping ions.
이때 POCL3개스를 이용해서 폴리실리콘에 도핑하기 위하여는 875t 정도의 고열이 필요하므로 이 공정진행중에 폴리실리콘 표면에 P2O5자연발생적으로 생긴다·At this time, high temperature of about 875t is required to dope polysilicon using POCL 3 gas, so P 2 O 5 occurs naturally on the surface of polysilicon during this process.
이 P2O5는 인(PHOSPHOROUS)이 함유된 산화막이기 때문에 흡습성이 강하므로 견고한 산화막질이 되지 못한다. 따라서 후 공정에서 자기정렬(SELF-ALIGN)용 마스크로 사용할 수 없고, 또한 마스크로 사용하기에는 흡습성이 많아서 P.R.을 도포했을때 접촉 불량으로 P.R.이 멀어지는 문제를 야기시킬 수 있다.Since P 2 O 5 is an oxide film containing phosphorus (PHOSPHOROUS), the hygroscopicity is strong, so that it is not a solid oxide film. Therefore, it cannot be used as a mask for self-alignment (SELF-ALIGN) in a later process, and also has a high hygroscopicity to be used as a mask, which may cause a problem in that the PR is far from contact when the PR is applied.
이러한 문제로 없애기 위하여 제1도(나)에 도시된 바와같이, P2O5를 HF를 사용해서 제거한 후, 자기정렬마스크용 산화막(4) 을 CVD(화학기 상증착법 )로 데포지션한다.In order to eliminate this problem, as shown in FIG. 1 (b), after removing P 2 O 5 using HF, the oxide film 4 for self-alignment mask is deposited by CVD (chemical vapor deposition).
그리고 게이트패턴을 정의하기 위하여 P.R.(5)을 코팅한다. 이어서 제1도(다)에 도시된 바와같이, 폴리실리콘 게이트 전극을 형성시키기 위해 사진식각공정으로 P.R.(5)을 정의하고, 이어서 제2도에(라)에 도시된 바와 같이, 산화막 건식식각장비를 이용하여 산화막(4)를 건식식각한다. 이어서, 측벽에 있는 폴리머를 제거하기 위해서 온도 약 40도, NH2OH : H2O2: H2O의 비가 대략 1 : 2 : 10되게 한 용액에서 세척을한다음, 폴리실리콘 전식각 정비를 이용하여 폴리실리콘(3)을 건식식각하여 폴리실리콘 게이트 전극(7)을 제조한다.And PR (5) is coated to define the gate pattern. Subsequently, as shown in FIG. 1 (C), PR (5) is defined by a photolithography process to form a polysilicon gate electrode, and then oxide dry etching as shown in FIG. 2 (D). Dry etching the oxide film (4) using the equipment. Subsequently, to remove the polymer on the sidewall, the solution is washed in a solution having a temperature of about 40 degrees and a ratio of about 1: 2: 10 of NH 2 OH: H 2 O 2 : H 2 O. The polysilicon 3 is dry-etched to produce the polysilicon gate electrode 7.
여기서 폴리실리콘을 SF6+탈프레온가스(F123)를 사용하여 에치하는데, 건식식각 장비의 조건을 대략M/W(마이크로웨이브) 파우워를 200mA, RF 파우워를 100W SF6농도를 20% 총유량 70SCCM, 코일전류 22A/5A, 온도 151C 등으로 정하여 식각한다. 이 때 선택도(SELECTIVITY)가 3 : 1 정도로 나빠서 CVD산화막을 폴리실리콘위에 두껍게 즉 2000 내지 3000Å 정도로 데포지션할 수 밖에 없다.Here, polysilicon is etched using SF 6 + defreon gas (F123), and the condition of dry etching equipment is about 200 mA for M / W (microwave) power and 20% for RF power for 100 W SF 6 concentration. Etch at a flow rate of 70SCCM, a coil current of 22A / 5A, and a temperature of 151C. At this time, the selectivity was poor at about 3: 1, so that the CVD oxide film was thickly deposited on polysilicon, that is, about 2000 to 3000 Pa.
그러다보니 다음 공정에서 게이트전극 부분과 여타 부분과의 단차가 높아져서 P.R, 코팅 후 마스크작업 할때 해상도를 떨어뜨리는 요인이 되었다.Therefore, in the next process, the step difference between the gate electrode part and other parts became high, which caused a drop in resolution when masking after P.R and coating.
본 발명은 실리콘 기판위에 게이트산화막을 형성하고, 그위에 폴리실리콘을 증착한 후, 폴리실리콘에 P이온을 도핑시키고, 자연히 발생된 P2O5를 제거한 후, 산화막을 형성하고, 사진식각공정으로 산화막 건식식각하고, 폴리실리콘을 건식식각하여 폴리실리콘 게이트 전극을 제조하는 방법에 있어서, P2O5제거후,곧바로 열산화를 시켜서 두께가 얇은 열산화막을 형성하고, 게이트 전극인 폴리실리콘을 식각할 때 CL₂를 사용하여 선택도를 크게하는 것이고, 열산화막은 산소를 이용하여 폴리실리콘위에 500 내지 600Å 성장시키는 것이며, 폴리실리콘 건식식각 장비를 이용하여 폴리실리콘과 산화막의 선택비는 약 30 : 1 이상인 CL₂의 저온/저이온에너지의 건식식각방법, 대략 M/W(마이크로웨이브) 파우워를 300mA, RF 파우워를 15W,CL₂120SCCM, 고일전류 20A/6A, 온도 -30℃ 등으로 정하여 식각하는 것이다.According to the present invention, a gate oxide film is formed on a silicon substrate, and polysilicon is deposited thereon, and then, the polysilicon is doped with P ions, the naturally occurring P 2 O 5 is removed, an oxide film is formed, and a photolithography process is performed. In the method of manufacturing a polysilicon gate electrode by dry etching the oxide and dry etching the polysilicon, after the removal of P 2 O 5 , thermal oxidation is performed immediately to form a thin thermal oxide film, and the polysilicon as a gate electrode is etched. In this case, the selectivity is increased by using CL ₂ , and the thermal oxide film is grown on the polysilicon by using 500 to 600Å on oxygen, and the selectivity ratio of polysilicon and oxide film is about 30: by using polysilicon dry etching equipment. Low temperature / low ion energy dry etching method of CL ₂ above 1, approx. 300 mA for M / W (microwave) power, 15 W for RF power, 120 scm for CL ₂ , high current The etching is performed at 20A / 6A, temperature -30 ° C or the like.
본 발명에서는 P2O5제거후 곧바로 온도 850℃∼950℃ 범위에서 일산화를 시켜서 두께가 얇은 산화막 500∼600Å을 형성하고 후 공정에서 자기정렬용 마스크패터닝할때 산화막 식각액 CL₂로 사용하여 선택도를 크게한다.To the present invention, the oxide film used as the etching liquid CL ₂ when the patterned mask for self-alignment in the P 2 O 5 and then removed after forming a straight temperature 850 ℃ ~950 a thin thickness in the range ℃ by monoxide oxide 500~600Å process selectivity Enlarge it.
본 발명은 제2도(가)에 도시된 바와 같이, 실리콘 기판(11)위에 게이트산화막(12)을 형성하고 그위에 폴리실리콘(13)을 증착한후 POCL3를 이용해서 폴리실리콘에 P이온을 도핑 시켜서 폴리실리콘 층이 도전성을 띄게 한다In the present invention, as shown in FIG. 2A, after forming the gate oxide film 12 on the silicon substrate 11 and depositing the polysilicon 13 thereon, P ions are formed on the polysilicon using POCL 3 . Doping to make the polysilicon layer conductive
그후에 P2O5를 HF를 사용해서 제거하고, 곧 바로 850 내지 950도의 로 내에서 산소를 이용하여 폴리실리콘위에 산화막(14)을 500 내지 600A 성장시킨다.Thereafter, P 2 O 5 is removed using HF, and 500 to 600 A of oxide film 14 is grown on polysilicon using oxygen in a furnace at 850 to 950 degrees.
다음에 제2도 (나)에 도시된 바와같이, 감광제(P.R )(15)를 도포하고, 제2도에 (다)에 도시된 바와같이 노광/현상을 과정을 거쳐서, 제2도 (라)에 도시된 바와같이 산화막 건식장비를 이용하여 산화막(14)를건식식각 한다. 이어서, 측벽에 있는 폴리머를 제거하기 위해서 온도 약 40도, NH4OH : H2O2: H2O의 비가 대략 1 : 2 : 10되게 한 용액에서 세척을 한다음, 폴리실리콘 건식각 정비를 이용하여 폴리실리콘(13)을 건식식각하여 폴리실리콘 게이트 전극(17)을 제조한다.Next, as shown in Fig. 2 (b), a photosensitive agent (PR) 15 is applied, and the exposure / development process is performed as shown in Fig. 2 (c). As shown in Figure 1), the oxide film 14 is dry-etched using the oxide film dry equipment. Subsequently, the polysilicon dry etch service is washed in a solution having a temperature of about 40 degrees and a ratio of about 1: 2: 10 of NH 4 OH: H 2 O 2 : H 2 O to remove the polymer on the sidewall. The polysilicon 13 is dry-etched to manufacture the polysilicon gate electrode 17.
이때 폴리실리콘 전식식각 장비를 이용 건식각을 할때, 폴리실리콘과 산화막의 선택비는 약 30 : 1 이상인 CL₂의 저온/저이온에너지의 건식식각장비를 이용한다.At this time, when dry etching using polysilicon electroetching equipment, the low temperature / low ion energy dry etching equipment of CL₂ having a selectivity ratio of polysilicon and oxide film is about 30: 1 or more.
여기서 폴리실리콘을 식각할패 CL₂ 저온/저이온에너지의 건식식각장비를 이용하는데 그 조건은, 대략 ECR 파우워를 300mA, RF 파우워를 15W, Cl2120 SCCM, 코일전류 20A/6A, 온도 -30℃등으로 정하여식각한다. 이렇게 하면 폴리실리콘 산화막의 식각비가 30 : 1 정도로 개선되고 폴리실리콘위의 산화막 500내지 600Å 정도로 되어 후공정에서의 여유도가 좋아진다.Here, the polysilicon is used to etch CL₂ low temperature / low ion dry etching equipment. The conditions are about 300mA of ECR power, 15W of RF power, Cl 2 120 SCCM, coil current 20A / 6A, temperature- Etch at 30 ℃ and so on. This improves the etch ratio of the polysilicon oxide film to about 30: 1 and improves the latitude in the post-processing process as the oxide film on the polysilicon is about 500 to 600 kPa.
이렇게 하므로써, 현재 기술에서는 CVD산화막을 중착시켜서 이를 건식각 후 폴리실리콘을 건식각하여 GATE 전극을 제조하여 스텝카브리지 문제가 해결되지 못하든 것이 본 발명에 의하여 해결될 수 있게 된것이다. 즉 제1도(라) 및 제2도 (라)에 도시된 바와 같이, CVD 산화막 2000 내지 3000Å이 열산화막500 내지 600Å으로 얇아지게 된다.In this way, in the current technology, it is possible to solve the problem of step-carbide by fabricating a GATE electrode by neutralizing a CVD oxide film and then etching the polysilicon and then dry-etching the polysilicon. That is, as shown in Figs. 1 (d) and 2 (d), the CVD oxide film 2000 to 3000 mV is thinned to the thermal oxide film 500 to 600 mV.
본 발명의 효과는, MOSFET의 폴리실리콘 GATE 전극을 형성시에 폴리실리콘을 증착후 인(P)도핑(POCL3DOPING)을 한 다음 인 산화막(P GLASS)을 불산을 통해서 제거후에 폴리실리콘위에 산소를 이용하여 산화막을 성장시킨 후, CVD 산화막을 증착시키지 않고 폴리실리콘위에 산화막을 성장시켜 폴리실리콘과 산화막의 선택비가 약 30 : 1 이상인 CL₂ BASE의 저온/저이온 에너지 ECR 건식각 장비를 이용하여 건식각을 한다. 그래서 CVD 산화막 두께가 없으므로 후공정에서 평탄화 효과가 크다.The effect of the present invention is that when forming polysilicon gate electrode of the MOSFET, polysilicon is deposited and then phosphorus (P) doped (POCL 3 DOPING), and then the phosphorus oxide film (P GLASS) is removed through hydrofluoric acid and oxygen on the polysilicon is removed. After the growth of the oxide film by using, the oxide film is grown on the polysilicon without depositing the CVD oxide film by using a low temperature / low ion energy ECR dry etching equipment of CL₂ BASE with a selectivity of polysilicon and oxide film of about 30: 1 or more. Etch. Therefore, since there is no CVD oxide film thickness, the planarization effect is large in a later process.
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| KR1019930004038A KR960006700B1 (en) | 1993-03-17 | 1993-03-17 | Manufacturing method of poly silicon gate electrode |
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