KR960006593A

KR960006593A - HDTV Scan Converter

Info

Publication number: KR960006593A
Application number: KR1019940018155A
Authority: KR
Inventors: 이창표
Original assignee: 이헌조; 엘지전자 주식회사
Priority date: 1994-07-26
Filing date: 1994-07-26
Publication date: 1996-02-23

Abstract

본 발명은 블럭단위로 입력되는 데이타를 영상크기에 관계없이 라인단위로 변환하도록 한 HDTV의 스캔변환 장치에 관한 것이다. 종래의 HDTV의 스캔변환장치는 영상의 크기가 변하면 사용이 불가능하던 점을 감안하여 본 발명은 라이트 및 리드 데이타가 저장되는 메모리 수단과, 상기 메모리수단이 데이타를 쓰기 위한 라이트 어드레스 발생용 바이너리 업 카운터수단과, 상기 메모리수단에서 라인단위로 데이타를 읽기위한 제1, 제2리드 어드레스 발생용 바이너리 업 카운터수단과, 라이트 및 리드 데이타가 사기 메모리 수단에 교대로 쓰여지게 하기 위한 라이트제어수단으로 구성되어 블럭단위로 입력되는 데이타를 라인단위로 변환시 입력영상의 크기가 변하여도 각종 데이타 동기신호들이 영상크기에 따라 변해준다면 회로의 수정없이 그대로 사용할 수 있도록 한 것이다.The present invention relates to an apparatus for scanning conversion of HDTV which converts data input in units of blocks into units of lines regardless of image size. In consideration of the fact that the conventional HDTV scan conversion apparatus cannot be used when the image size is changed, the present invention provides a memory means for storing write and read data, and a binary up counter for write address generation for writing the data by the memory means. Means, first and second lead address generation binary up counter means for reading data on a line-by-line basis from the memory means, and write control means for causing write and read data to be alternately written to the fraudulent memory means. When data input in block unit is converted into line unit, even if the size of input image changes, if various data synchronization signals change according to image size, it can be used without modification of circuit.

Description

HDTV Scan Converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 구성도.1 is a conventional configuration diagram.

제2도는 제1도에 따른 입출력 데이타 형태를 나타낸 도면.FIG. 2 is a diagram showing input and output data types according to FIG. 1. FIG.

제3도는 본 발명의 구성도.3 is a block diagram of the present invention.

Claims

Memory means for storing write and read data, Binary up counter means for write address generation by which said memory means writes data, Binary for generating first and second lead addresses for reading data in line units from said memory means. And an up counter means and write control means for causing write and read data to be written alternately to fraudulent memory means.

The apparatus of claim 1, wherein the memory means is dual port RAM.

2. The apparatus as claimed in claim 1, wherein the binary up counter means for generating the first lead address is a horizontal read counter means.

2. The apparatus as claimed in claim 1, wherein the second up address generating binary up counter means is a vertical reading counter means.

2. The write control means according to claim 1, wherein the write control means comprises a T flip flop and an inverter connected to the T flip flop to toggle the best address values of the memory means so that the written data and the read data cannot exist in the same memory address. Scan conversion device of the HDTV, characterized in that.

※ Note: The disclosure is based on the initial application.