KR960006111B1 - Thin film transistor manufacturing process - Google Patents
Thin film transistor manufacturing process Download PDFInfo
- Publication number
- KR960006111B1 KR960006111B1 KR1019920026370A KR920026370A KR960006111B1 KR 960006111 B1 KR960006111 B1 KR 960006111B1 KR 1019920026370 A KR1019920026370 A KR 1019920026370A KR 920026370 A KR920026370 A KR 920026370A KR 960006111 B1 KR960006111 B1 KR 960006111B1
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- KR
- South Korea
- Prior art keywords
- forming
- active layer
- thin film
- film transistor
- contact resistance
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title description 22
- 238000004519 manufacturing process Methods 0.000 title description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
제1도는 종래의 박막트랜지스터 평면도.1 is a plan view of a conventional thin film transistor.
제2도는 제1도의 A-A'선상 단면도2 is a cross-sectional view along the line A-A 'of FIG.
제3도는 본 발명의 박막트랜지스터 평면도.3 is a plan view of a thin film transistor of the present invention.
제4도는 제4도의 B-B'선상 단면도.4 is a cross-sectional view along the line B-B 'in FIG.
제5도는 본 발명 박막트랜지스터 공정 단면도.5 is a cross-sectional view of a thin film transistor process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
l : 게이트전극 2 : 소오스/드레인전극l: gate electrode 2: source / drain electrode
3 : 활성층 4 : 절연막3: active layer 4: insulating film
5 : 접촉저항층 6 : 기판5: contact resistance layer 6: substrate
7 : 감광막7: photosensitive film
본 발명은 액정표시 장치등의 구동 스위치로 이용되는 박막트랜지스터에 관한 것으로, 특히 접촉저항층을 이온주입으로 형성하는 박막트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as a drive switch of a liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor in which a contact resistance layer is formed by ion implantation.
종래의 박막트랜지스터 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional thin film transistor manufacturing method is as follows.
제1도는 종래의 박막트랜지스터 평면도이고, 제2도는 제1도의 A-A'선상 단면도로써, 제조방법은 유리 또는 석영기판(6) 위에 금속을 증착하고, 패터닝하여 게이트 전극(1)을 형성한 다음 전면에 절연막(4)을 증착한다.FIG. 1 is a plan view of a conventional thin film transistor, and FIG. 2 is a cross-sectional view taken along the line A-A 'of FIG. 1, and a method of manufacturing the gate electrode 1 is formed by depositing and patterning a metal on a glass or quartz substrate 6. Next, an insulating film 4 is deposited on the entire surface.
그리고 절연막(4) 위에 반도체 물질과, n+형 반도체 물질을 차례로 증착하고 패터닝하여 활성층(3)과 접촉저항층(5)을 형성한 다음, 금속을 증착하고 페터닝하여 소오스/드레인전극(2)을 형성한 후 패널영역의 접촉저항층(5)을 제거하므로 종래의 박막트랜지스터를 제조한다.Then, the semiconductor material and the n + type semiconductor material are deposited and patterned on the insulating film 4 in order to form the active layer 3 and the contact resistance layer 5, and then the metal is deposited and patterned to obtain the source / drain electrodes 2. ), The contact resistance layer 5 of the panel region is removed, thereby manufacturing a conventional thin film transistor.
이와 같은 종래의 박막트랜지스터에 있어서 접촉저항층(5)을 활성층(3)과 소오스/드레인전극(2)간의 접촉저항을 감소시키기 위해 원조주기율 표의 5족 원소가 도핑된 n+층으로 형성하여 전도율이 높도록 하였다.In such a conventional thin film transistor, the contact resistance layer 5 is formed of an n + layer doped with a Group 5 element of the aid periodic table to reduce the contact resistance between the active layer 3 and the source / drain electrodes 2. Was made high.
그러나 상기 종래의 박막트랜지스터 제조방법에 있어서는 소오스/드레인전극(2)을 형성하고 채널영역의 접촉저항층(5)을 제거하는데 이때 접촉저항층(5)이 완전히 식각되지 못하고 잔류하면 박막트랜지스터의 게이트전극(1)에 신호전압이 인가되지 않는 상태에도 도전율이 높은 접촉저항층(5)의 잔류로 인해 누설잔류가 흐를 수 있고, 또한 접촉저항층(5)을 식각할때 접촉저항층(5)내에 도핑된 n+원소가 활성층(3)으로 확산되어 소자 특성이 저하될 수 있으며, 이를 해결하기 위하여 n+원소가 활산된 활성층(5)영역을 식각할때 식각깊이가 과도할 경우, 활성층(3) 두께가 얇아져서 게이트전극에 신호전압이 인가된 온(ON)상태에서도 문턱전압이 증가하고 전류값은 감소되어 박막트랜지스터의 전기적 특성이 악화되는 등의 문제점이 있다.However, in the conventional thin film transistor manufacturing method, the source / drain electrodes 2 are formed and the contact resistance layer 5 of the channel region is removed. If the contact resistance layer 5 is not etched completely, the gate of the thin film transistor is left. Even in the state in which the signal voltage is not applied to the electrode 1, the residual of the contact resistance layer 5 with high conductivity may flow, and when the contact resistance layer 5 is etched, the contact resistance layer 5 The doped n + element may diffuse into the active layer 3 to deteriorate device characteristics. In order to solve this problem, when the etching depth is excessive when the n + element is active, the active layer ( 3) As the thickness becomes thin, there is a problem that the threshold voltage increases and the current value decreases even when the signal voltage is applied to the gate electrode, thereby deteriorating the electrical characteristics of the thin film transistor.
본 발명의 상기의 문제점을 해결하기 위하여 안출한 것으로, 접촉저항층 형성시에 의한 박막트랜지스터의 전기적 특성의 악화를 해결하는데 그 목적이 있다.In order to solve the above problems of the present invention, an object thereof is to solve the deterioration of the electrical characteristics of the thin film transistor due to the formation of the contact resistance layer.
이와 같은 목적을 달성하기 위한 본 발명은 게이트전극과 활성층을 형성하는 채널영역에 마스크를 형성하여 n+이온주입하여 접촉저항층을 형성하는 박막트랜지스터 제조방법이다.The present invention for achieving the above object is a thin film transistor manufacturing method for forming a contact resistance layer by forming a mask in the channel region forming the gate electrode and the active layer by implanting n + ions.
이와 같은 본 발명의 박막트랜지스터을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Referring to the thin film transistor of the present invention as described above in more detail as follows.
즉, 제3도는 본 발명의 박막트랜지스터 평면도이고, 제4도는 제3도의 B-B'선상 단면도로써, 박막트랜지스터의 구조는 종래와 거의 같으나, 제5도는 본 발명의 박막트랜지스터 공정단면도로써, 본 발명의 박막트랜지스터 제조방법은 제5도(a)와 같이 유리 또는 석영기판(6)에 금속을 증착하고 포토에치 공정으로 패너닝하여 게이트전극(1)을 형성한 후, 전면에 절연막(4)을 증착하고 반도체층으로 게이트전극(1) 상부의절연막(4) 위에 활성층(3)을 형성한 다음, 네가티브형 감광막(7)을 증착하고 소오스/드레인 마스크를 이용하여 노광 및 현상한다.That is, FIG. 3 is a plan view of the thin film transistor of the present invention, and FIG. 4 is a cross-sectional view taken along line B-B 'of FIG. 3, and the structure of the thin film transistor is almost the same as in the related art, but FIG. 5 is a process cross-sectional view of the thin film transistor of the present invention. In the method of manufacturing a thin film transistor of the present invention, as shown in FIG. 5 (a), a metal is deposited on a glass or quartz substrate 6 and panned by a photoetch process to form a gate electrode 1, and then an insulating film 4 ), The active layer 3 is formed on the insulating film 4 on the gate electrode 1 as a semiconductor layer, and then the negative photosensitive film 7 is deposited and exposed and developed using a source / drain mask.
제5도(b)와 같이 형성된 감광막(7) 마스크를 이용하여 활성층(3) 표면에 고농도 n형 이온주입을 실시한다High concentration n-type ion implantation is performed on the surface of the active layer 3 using the photosensitive film 7 mask formed as shown in FIG.
그리고 제5도(c)와 같이 감광막(7)을 제거한 뒤, 금속을 증착하고 소오스/드레인 마스크를 이용한 포토에치 공정으로 소오스/드레인 전극(2)을 형성하여 본 발명의 박막트랜지스터를 제작한다.After removing the photoresist film 7 as shown in FIG. 5C, a metal is deposited and a source / drain electrode 2 is formed by a photoetch process using a source / drain mask to manufacture the thin film transistor of the present invention. .
이상에서 설명한 바와 같이 본 발명의 박막트랜지스터 제조방법에 있어서는 접촉저항층(5)을 선택적인 이온주입에 의해 형성하므로써, 식각공정이 필요없고 종래의 식각공정으로 인한 문턱전압 및 오프(off)전류 증가와, 온전류 감소등의 전기적 특성 악화를 방지할 수 있으며 이온주입 공정으로 더욱 높은 전도율을 갖는 접촉저항층이 형성되므로 소오스/드레인 전극과 활성층 사이의 접촉저항이 감소되는 등의 효과가 있다.As described above, in the method of manufacturing the thin film transistor of the present invention, the contact resistance layer 5 is formed by selective ion implantation, thereby eliminating the etching process and increasing the threshold voltage and off current due to the conventional etching process. Deterioration of electrical characteristics such as a decrease in on-current can be prevented, and a contact resistance layer having a higher conductivity is formed by an ion implantation process, thereby reducing the contact resistance between the source / drain electrodes and the active layer.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920026370A KR960006111B1 (en) | 1992-12-30 | 1992-12-30 | Thin film transistor manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920026370A KR960006111B1 (en) | 1992-12-30 | 1992-12-30 | Thin film transistor manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940016917A KR940016917A (en) | 1994-07-25 |
| KR960006111B1 true KR960006111B1 (en) | 1996-05-08 |
Family
ID=19347497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920026370A KR960006111B1 (en) | 1992-12-30 | 1992-12-30 | Thin film transistor manufacturing process |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960006111B1 (en) |
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1992
- 1992-12-30 KR KR1019920026370A patent/KR960006111B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR940016917A (en) | 1994-07-25 |
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