KR960006003A - Manufacturing method of CMOS transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to CMOS transistors, and more particularly to a method for fabricating CMOS transistors that is suitable for simplification of the process and for reducing the chip size to improve integration. To this end, the present invention defines a field region and an active region on a first conductive engine to form a field oxide film and an isolation oxide film on the field region, and a second conductive well on the active region of the first conductive substrate. Forming a high concentration first conductive impurity layer in source / drain regions on both sides of the second conductive well channel region, and source / drain regions on both sides of the first conductive substrate channel region A fourth step of forming a high concentration second conductive impurity layer in the second process, and forming a trench by etching the first conductive substrate and the second conductive well in the middle portion of the channel region of the high concentration first and second conductive impurity layers A fifth step of forming a gate electrode through the trench to an upper height of the isolation oxide layer; and a seventh hole selectively forming a contact hole to expose the high concentration first and second conductive impurity layers by depositing an insulating film on the entire surface thereof. , In contact with the exposed heavily doped first and second conductivity type impurity layer through the contact holes, including an eighth step of forming a metal layer characterized by a formed.

Description

Manufacturing method of CMOS transistor

As this is a public information case, the full text was not included.

2A to 2F show a method of manufacturing a CMOS transistor of the present invention.

Claims (5)

A first step of forming a field oxide layer and an isolation oxide layer in the field region by defining a field region and an active region on the first conductive substrate, and a second conductive well in the active region of the first conductive substrate; Process, forming a high concentration first conductive impurity layer in source / drain regions on both sides of the second conductive well channel region, and source / drain region high concentration second conductivity on both sides of the first conductive substrate channel region A fourth step of forming an impurity layer, a fifth step of forming a trench by etching the first conductive substrate and the second conductive well in the middle portion of the channel region of the high concentration first and second conductivity type impurity layer, and the trench A sixth step of forming a gate electrode up to an upper height of the isolation oxide film through the deposition process; and a seventh step of selectively forming a contact hole to expose the high concentration first and second conductive impurity layers by depositing an insulating film on the entire surface thereof. through And an eighth step of forming a metal layer to be in contact with the exposed high concentration first and second degree typical impurity layers. The method of claim 1, wherein the first conductive type is P type and the second conductive type is n type. The method of claim 1, wherein the trench is formed by etching the first conductive substrate and the second conductive well to a depth of a high concentration of the first and second degree impurity layers. The method of claim 1, wherein a low concentration first conductive impurity layer is further formed on the high concentration first typical impurity layer. The method of claim 1, wherein the second concentration impurity layer is further formed in the second concentration impurity layer. ※ Note: The disclosure is based on the initial application.