KR970053807A - Junction Capacitor Using Bipolar Transistor Structure and Its Manufacturing Method - Google Patents

Junction Capacitor Using Bipolar Transistor Structure and Its Manufacturing Method Download PDF

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KR970053807A
KR970053807A KR1019950047988A KR19950047988A KR970053807A KR 970053807 A KR970053807 A KR 970053807A KR 1019950047988 A KR1019950047988 A KR 1019950047988A KR 19950047988 A KR19950047988 A KR 19950047988A KR 970053807 A KR970053807 A KR 970053807A
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region
conductive
conductivity type
type region
isolation
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KR1019950047988A
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KR100247281B1 (en
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유준형
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김광호
삼선전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 트랜지스터의 접합 정전 용량값을 향상 시키기위한 제조공정에 관한것 으로서 반도체 기판 위에 매몰층을 형성하고, 상기 매몰층 위에 에피층을 형성하고, 상기 에피층에 격리 영역을 형성한 다음 상기 에피층에 상기 격리 영역과 중첩하도록 제1 도전형 영역을 형성하고, 상기 제1 도전형 영역과 일부만 중첩하도록 제2 도전형 영역을 형성하는 접합 축전기의 제조 방법으로서, 이때 제1 도전형 영역이 P형 절연체와 연결되고 제1 도전형 영역 안에 형성되는 제2 도전형 영역의 일부가 제1 도전형 영역을 벗어나 N형의 에피 영역과 접속되게 하는 구조로서 이미터-베이스, 콜렉터-베이스, 콜렉터-기판 사이에 형성되는 접합 용량이 병렬로 형성 되게함으로서 동일한 면적에서 더 큰 정전 용량값을 얻는 효과가 있다.The present invention relates to a fabrication process for improving a junction capacitance value of a transistor, wherein the buried layer is formed on a semiconductor substrate, an epitaxial layer is formed on the buried layer, and an isolation region is formed on the epitaxial layer. A method of manufacturing a junction capacitor in which a first conductivity type region is formed in a layer so as to overlap with the isolation region, and a second conductivity type region is formed so as to partially overlap the first conductivity type region, wherein the first conductivity type region is P. A part of the second conductive type region which is connected to the type insulator and is formed in the first conductive type region to leave the first conductive type region and is connected to the N type epi region. By allowing the junction capacitances formed between the substrates to be formed in parallel, there is an effect of obtaining a larger capacitance value in the same area.

Description

바이폴라 트랜지스터 구조를 이용한 접합 축전기 및 그 제조 방법Junction Capacitor Using Bipolar Transistor Structure and Its Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 실시예에 따른 접합 축전기의 단면도이고,4 is a cross-sectional view of a junction capacitor according to an embodiment of the present invention,

Claims (5)

제1 도전형의 반도체 기판,A first conductive semiconductor substrate, 상기 기판 위에 형성되어 있는 제2 도전형 매몰층,A second conductive buried layer formed on the substrate, 상기 매몰층 위에 형성되어 있는 제2 도전형의 반도체층,A second conductive semiconductor layer formed on the buried layer, 상기 매몰층 양쪽에 상기 기판과 닿도록 상기 반도체층에 형성되어 있는 제1 도전형의 격리 영역,Isolation regions of a first conductivity type formed in the semiconductor layer so as to contact the substrate on both sides of the buried layer, 상기 격리 영역 사이의 상기 반도체층에 형성되어 있으며 상기 격리 영여과 연결되어 있는 제1 도전형 영역,A first conductivity type region formed in the semiconductor layer between the isolation regions and connected to the isolation region, 상기 제1 도전형 영역에 형성되어 있으며 상기 반도체층과 연결되어 있는 제2 도전형 영역을 포함하는 접합 축전기A junction capacitor formed in the first conductivity type region and including a second conductivity type region connected to the semiconductor layer. 제1항에 있어서,The method of claim 1, 상기 제2 도전형 영역과 접속되어 있는 제1 전극,A first electrode connected to the second conductivity type region, 상기 제1 도전형 영역 또는 상기 격리 영역과 접속되어 있는 제2 전극을 더 포함하는 접합 축전기.And a second electrode connected to the first conductivity type region or the isolation region. 제2항에서In claim 2 상기 제2 전극은 상기 제1 도전형 영역과 상기 격리 영역의 연결 부분과 접속되어 있는 접합 축전기.And the second electrode is connected to a connection portion between the first conductivity type region and the isolation region. 반도체 기판 위에 매몰층을 형성하는 제1 단계,A first step of forming a buried layer on a semiconductor substrate, 상기 매몰층 위에 에피층을 형성하고 상기 에피층에 이온을 주입 확산하여 격리 영역을 형성하는 제2 단계,Forming an epitaxial layer on the buried layer and implanting and diffusing ions into the epitaxial layer to form an isolation region; 상기 에피층에 상기 격리 영역과 중첩하도록 제1 도전형 영역을 형성하고, 상기 제1 도전형 영역과 일부만 중첩하도록 제2 도전형 영역을 형성하는 제3 단계를 포함하는 접합 축전기의 제조 방법.And forming a first conductive region in the epitaxial layer so as to overlap the isolation region, and forming a second conductive region so as to partially overlap the first conductive region. 제4항에서,In claim 4, 절연막을 형성하고 패터닝하여 상기 제1 도전형 영역 안의 상기 제2 도전형 영역 및 상기 제1 도전형 영역과 상기 격리 영역의 일부를 드러내는 접촉홈을 형성하는 단계,Forming and patterning an insulating film to form a contact groove exposing the second conductive region and the first conductive region and a portion of the isolation region in the first conductive region, 도전 물질을 적층하고 패터닝하여 상기 제2 도전형 영역과 접속되는 제1 전극과 상기 제1 도전형 영역 또는 상기 격리 영역과 접속되는 제2 전극을 형성하는 단계를 더 포함하는 접합 축전기의 제조 방법.Stacking and patterning a conductive material to form a first electrode connected to the second conductive region and a second electrode connected to the first conductive region or the isolation region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047988A 1995-12-08 1995-12-08 Junction capacitor using bipolar transistor structure and manufacturing method thereof KR100247281B1 (en)

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KR1019950047988A KR100247281B1 (en) 1995-12-08 1995-12-08 Junction capacitor using bipolar transistor structure and manufacturing method thereof

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KR970053807A true KR970053807A (en) 1997-07-31
KR100247281B1 KR100247281B1 (en) 2000-03-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100852576B1 (en) * 2006-04-24 2008-08-18 산요덴키가부시키가이샤 Semiconductor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100852576B1 (en) * 2006-04-24 2008-08-18 산요덴키가부시키가이샤 Semiconductor device and method for manufacturing the same

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