KR960005978B1 - Serial communication circuit - Google Patents

Abstract

The circuit transmits data in high speed and is of use especially for retransmission. It includes following components. Latches(LT1~LT8) are connected parellel to data bus and they store or read data from a data bus and an input buffer(11). A clock counter(13) counts the number of clocks from a clock generator(12). Decoder(16) controls the output of latches(LT1~LT8) by decoding the value of clock count. Latch buffer(14) temporarily stores the output of latches and generates them by clock. Clock output buffer(15) controls the output of the clock generator(12) by clock output control signal from the clock counter(13).

Description

Serial communication circuit

1 is a conventional serial communication circuit diagram.

2 is a serial communication circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

11: input buffer 12: clock generator

13: Clock counter 14: Data output latch buffer

15: clock output buffer 16: decoder

LT1 ~ LT8: Latch DATA BUS: Data Bus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication circuit, and more particularly, to a serial communication circuit in which a circuit is simply configured to be suitable for high speed operation.

In the conventional serial communication circuit, as shown in FIG. 1, a shift register that is serially connected by the number of bits of data to be transmitted, receives data from the front end according to a clock input, and sends the data that it has to the next step. REG1 to REG7, a data bus connected to the data input terminals of the shift registers REG1 to REG7 to load data or output data to a system according to a control signal, and the shift registers REG1 to REG7. A clock generator 2 connected to the clock input terminal CK of the circuit board 2 to supply a clock, and a clock counter 3 to count how many clocks are supplied from the clock generator 2 to the shift registers REG1 to REG7. ), A data output latch buffer 4 for temporarily latching and transmitting the outputs of the shift registers REG1 to REG7, and a clock output generated from the clock generator 3. It is composed of a clock output buffer (5). Here, reference numeral 1 is an input buffer.

In the conventional circuit configured as described above, the 8-bit serial communication circuit will be described. As data is input through the input buffer 1, each of the shift registers REG1 to REG7 is outputted from the clock generator 2. In response to the clock input terminal CK, it accepts the output of the previous shift register and transfers its data to the next stage.

When the data thus transmitted is input to the data output latch buffer 4, the data output latch buffer 4 also temporarily receives the input data as the clock output terminal CK receives the clock output from the clock generator 2 as well. Save and output sequentially.

At this time, it can be known whether the clock counter 3 counts the number of clocks output from the clock generator 2 to the clock input terminal CK of each shift register REG1 to REG7. When the clock counter 3 counts the number of clocks and outputs the clock output control signal to the clock output buffer 5, the clock output buffer 5 controls and outputs the clock output.

However, in such a conventional circuit, in shifting data sequentially to a next shift register using a shift register, the circuit of the shift register is complicated, and the transfer of data in the rise time and the fall time of the clock pulse is multiple shifts. The clock generator needs to be well built because it can skip registers all at once and is not suitable for high speed operation. In addition, there was a problem in that the data was shifted during the data transmission, and thus the data was different from the initially set value.

Accordingly, an object of the present invention is to provide a serial communication circuit that is very useful when retransmission is required by allowing data stored in a latch to be stored unchanged during serial transmission.

Another object of the present invention is to provide a serial communication circuit that is suitable for high-speed operation and can easily implement a circuit such that a plurality of data do not occur at once, such as a shift register.

The circuit for achieving the object of the present invention, as shown in Figure 2, writes the data to be transmitted, or as much as the beast of the data to be transmitted to read the data received through the data bus (DATA BUS) and the input buffer 11 A latch LT1 to LT8 connected in parallel to the data bus, a clock counter 13 for counting the number of clocks output from the clock generator 12, and a count value of the clock counter 13 is decoded. Decoder 16 for controlling the outputs of the latches LT1 to LT8, a data output latch buffer 14 for temporarily storing the outputs of the latches LT1 to LT8 and outputting them according to a clock, The clock output buffer 15 controls the clock output of the clock generator 12 according to the clock output control signal generated from the clock counter 13.

Referring to the operation and effects of the present invention configured as described above in detail.

In this case, the latch is assuming that data to be transmitted is 8-bit data. The data to be transmitted from the data bus of the system is stored in the latches LT1 to LT8 or inputted through the input buffer 11. In the state where the data is stored, when the clock is generated by the clock generator 12, the number of clocks inputted from the clock counter 13 is counted, and the counted value is output to the decoder 16 and the clock generation control signal. The clock output control signals to the clock generator 12 are output to the clock output buffer 15, respectively.

Accordingly, the decoder 16 outputs a control signal of each latch which decodes the count value output from the clock counter 13 to the latches LT7-LT8. Then, the latches LT1-LT8 transfer the output data thereof to the input terminal IN of the data output latch buffer 14 by an input control signal. The data output latch buffer 14 receiving the data from the latches LT1-LT8 finally outputs the data according to the clock input from the clock generator 12 to the clock terminal CK.

As the clock counter 13 counts the clock generated by the clock generator 12 as described above, the decoder 16 sequentially sends a control signal to each of the latches LT1-LT8 and receives a control signal. LT1-LT8 sends its data to the data output latch buffer 14, and the data of the data output latch buffer 14 is output as the output of the serial transmission circuit.

That is, data to be transmitted in the data bus of the system is stored in the latches LT1-LT8, and the output of the decoder 16 is input to each latch LT1-LT8 as a control signal. The decoder 16 controls to output one latch (LT1-LT8) output data to the data output latch buffer 14 according to the output of the clock counter 13. At this time, as the clock is generated, the clock counter 13 counts the number of clocks. As a result, the decoder 16 sequentially controls the latches LT1-LT8 so that data to be transmitted is sequentially outputted from the data output latch buffer 14. Will output via When receiving data, it operates in the same way and input data is sequentially stored in each latch (LT1-LT8).

As described in detail above, the present invention is very useful when the data stored in each latch does not change during serial transmission and needs to be retransmitted due to a problem occurring during transmission. Since the data does not occur at the same time as a shift register, a plurality of data do not occur at once. The operation is possible, and the circuit has a simple effect to minimize the area.

Claims (1)

A latch connected in parallel to the data bus as much as a beast of data to be transmitted to store data received through a data bus or a data received through an input buffer and output to the data bus according to a control signal; A clock counter that counts the number of clocks generated and output from a clock generator, a decoder which decodes the count value of the clock counter and sequentially outputs one of the latches, and outputs the latches output from the clock generator Data output latch buffer for storing and output according to the clock, and a clock output buffer for outputting the clock generated by the clock generator to the outside in accordance with the clock output control signal generated from the clock counter. Serial communication circuit.