KR0171939B1 - Random accessible fifo resistor - Google Patents

Abstract

The random accessible FIFO of the present invention is different from the conventional FIFO shifting, storing, and outputting an input by a clock signal having a certain period, and then controlling it from the outside after inputting it to a suitable place according to a control signal from the outside By outputting the signal, the device can be used efficiently and offers the advantage of fast and accurate data transfer.

Description

Random Accessible First-In-First-Out Register

1 is a circuit diagram showing a conventional first-in, first-out register.

2 is a circuit diagram illustrating a random accessible first-in first-out register according to an embodiment of the present invention.

3 is a block diagram showing a portion of a peripheral circuit for controlling FIG.

* Explanation of symbols for main parts of the drawings

1 ~ 4: Bus line 5 ~ 8,70,72: Output line

9 ~ 12,54 ~ 60: Register 21 ~ 24: AND gate

31 ~ 34: S-R flip flop 52: 2 to 4 decoders

62: 4 units 1 multiplexer 64: 2 units 1 multiplexer

74 ~ 80: Input line

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to first-in-first-out (FIFO) registers that interface data or instructions between two different logics of timing in semiconductor devices. More specifically, the present invention relates to data by randomly processing data. Is a random access first-in, first-out register that transmits fast and precisely.

Conventional first-in, first-out registers are connected between I / O devices in the semiconductor autonomy and peripheral devices, to match the different data processing speeds of the peripheral device and the semiconductor or in and inside the semiconductor.

FIG. 1 is a circuit diagram showing a conventional first-in first-out register, in which four 8-bit bus lines 1 to 4 for simultaneously inputting data and data from the 8-bit bus lines 1 to 4 are stored for a predetermined time. A first register 9, a second register 10, a third register 11, and a fourth register 12 cascaded to the first register 9 in series, and the fourth register 12. Output lines 5 to 8 for outputting signals from the < RTI ID = 0.0 >

The 8-bit bus lines 1 to 4 respectively input 8-bit data at the same time, and eventually transmit 32-bit signals simultaneously.

Each of the first, second, third, and fourth registers includes 32 latches, respectively, and simultaneously processes 32-bit signals.

The FIFO shifter register further includes a clock signal supply unit 40 for supplying a clock signal to each of the registers 9-12.

The clock signal supply unit 40 inputs an input line 35 for inputting an input standby signal from an external source, an input line 25 for inputting an input drive signal from an external source, and the light standby signal and a light drive signal. An AND gate 21 for AND-combining, a first SR flip-flop 31 for making the signal from the AND gate 21 an S input, and an R input for the first S-R flip-flop 31 for S input The second SR flip-flop 32 and the third SR flip-flop 33 whose R inputs are the S inputs, and a control signal are externally input in the last period of the clock signal. A fourth SR flip-flop 34 with the R input of the third control line 38, the third SR flip-flop 33 as the S input, and the R input of the signal on the control line 38; An output line 37 for supplying the authenticity signal from the 4 SR flip-flop 34 to the outside as an output standby signal; and the first, second, third and fourth An input line 36 for inputting a signal for initializing the S-R flip-flops 31 to 34 is provided.

In addition, the clock signal supply unit 40 includes an AND gate 22 which AND-combines the authenticity signal from the first register 31 and the complementary signal from the second register 32, and the first signal. An AND gate 23 for AND combining the authenticity signal from the second register 32 and the complementary signal from the third register 33, and an inverter for inverting the signal from the control line 38. And an AND gate 24 for AND combining the authenticity signal from the third register 33, the complementary signal from the fourth register 34, and the signal from the inverter 39. ) Is further provided.

Initially, the first to fourth flip-flops 31 to 34 maintain a true state (high state) of the output terminal of the authenticity (output state of repair) by the initialization signal from the input line 36.

The AND gate 21 AND-combines the signal on the high level input line 35 and the signal on the input line 25 to generate a high level first clock. The first clock drives the first register 9 to supply a signal to the second register 10. At the same time, the first S-R flip-flop 31 is in a high state and supplies a signal to the AND gate 22. The first S-R flip-flop 31 resets the first clock to a low level using the signal from the AND gate 22 as an R input.

In addition, the second flip-flop 32 drives the second register 10 by the high level signal from the AND gate 22 and is initialized by the signal from the AND gate 23. It is in the same state.

The AND gate 24 receives the low level signal on the control line 38 to drive the fourth register 12 to output the input data to the outside. Thereafter, the high level clock on the control line 38 is input to reset the fourth clock signal.

However, the shift registers (i.e., the first to fourth registers) have a problem in that data access time is slow initially and unnecessary register portions are generated.

This is because the data input through the data line is supplied to the final output line through the multi-stage register.

Accordingly, an object of the present invention is to provide a random accessible FIFO register capable of transmitting data at high speed and efficiently using a device.

In order to achieve the above object, the random accessible FIFO register according to the present invention has an input line for parallel input of an N-bit signal from the outside and the N-bit signal from the input line in common. Two or more registers that are temporarily received and stored, driving means for driving the two or more registers by a control signal from an external device, and a first signal for selecting any one of the output signals of the two or more registers. Selecting means and second selecting means for selectively outputting an N-bit signal from the input line and an N-bit signal from the first signal selecting means by a drive signal from the outside.

Hereinafter, with reference to the drawings related to the present invention will be described in detail.

2 is a circuit diagram showing an embodiment of the random access first-in first-out register of the present invention, the input line 50 for inputting N-bit data from the outside, and on the input line 50 A first register 54 for inputting and storing an N-bit signal, a second register 56 for inputting and storing an N-bit signal on the input line 50, and on the input line 50; A third register 58 for inputting and storing an N-bit signal, a fourth register 60 for inputting and storing an N-bit signal on the input line 50, and a control signal from the outside ( And a two-to-four decoder 52 that decodes I0 and I1 and supplies driving signals to the first to fourth registers 54 to 60.

Each of the first to fourth registers 54 to 60 includes N latches capable of latching one bit of data.

The random accessible FIFO register may include the first latch group 54, the second latch group 56, the third latch group 58, and the fourth according to the control signals S0 and S1 from the outside. A four-to-one multiplexer 62 multiplexing signals from the latch group 60, and the input line 50 and the four-to-one multiplexer 62 according to a driving signal F-EN from the outside. Further provided are two-to-one multiplexers 64 for multiplexing the signals from. The driving signal F-EN is an entire driving signal of the random accessible FIFO register. At the same time the drive signal F-EN becomes high, the four-to-one multiplexer 62 drives to read data stored in a register.

3 is a block diagram showing a portion of a peripheral circuit for controlling the random access FIFO register.

3 shows the control signals I0 and I1 from the input lines 74 and 76 and the control signals S0 and S1 from the input lines 78 and 80 to read the last data and then write the next data. The read control signal generator 82 generates a read-empty signal through the output line 70 when the read operation is suspended until the data to be read is no longer left in the latch. And a write-full signal generated through the output line 72 when no more data is received by receiving the control signals I0 and I1 and the control signals S0 and S1. The light control signal generator 84 is provided.

Let's look at the operation of the random access FIFO register. When N-bit data is input to the input line 50 in the initial state, the two-to-four decoder 52 decodes the low-level control signals I0 and I1 so as to decode the first register. 54) to write the N-bit data. The four-to-one multiplexer 62 multiplexes the N-bit data from the first register 54 by the low-level control signals S0 and S1. At the same time, the external driving signal F-EN drives the two-to-one multiplexer 64 to output N-bit data from the first register 54.

While data from the first register 54 is being output, the second N-bit data from the outside is inputted and written to the second register 56. At this time, the two-to-four decoder 52 decodes the low level I0 and the high level I1 signals and supplies N-bit data to the second register 56. Further, the third N-bit data (fourth N-bit data) is stored in the third register (fourth register).

At this time, when data from the first register 54 is continuously output, the write operation is stopped by the write-full signal from the write control signal generator 84.

The four-to-one multiplexer 62 is continuously driven by control signals S0 and S1 from the outside to output data from the fourth register 60.

After the read operation, the singer read control signal generator 82 generates a read empty signal (Read-empty) to stop the read operation.

After generation of the read-empty signal (Read-empty), any number of N-bit data is input again from the outside to perform the above write operation and read operation.

However, if the last data is written in the second latch group 56 and not in the fourth latch group 60, the read-amplifier signal (if the data from the third register 58 is still being outputted). The data write operation starting after the occurrence of Read-empty is performed in the order of the third latch group 58, the fourth latch group 60, the first latch group 54, the second latch group 56, and so on. Is performed.

As described above, the random accessible first-in first-out register of the present invention is different from the conventional first-in first-out register in a suitable place according to a control signal from the outside, while shifting and storing and outputting an input by a clock signal having a certain period. By inputting and outputting it according to the control signal from the outside, the device can be used efficiently and provides the advantage of transmitting data quickly and accurately.

Claims (1)

An input line for inputting N-bit signals from outside in parallel, two or more registers for temporarily receiving and storing the N-bit signals from the input lines in common, and controlling from the outside Drive means for driving the two or more registers by a signal, first signal selecting means for selecting any one of the output signals of the two or more registers, and a drive signal from the outside from the input line And a second selection means for selectively outputting an N-bit signal and an N-bit signal from said first signal selection means.