KR19980043765A - High Speed Serial Communication Circuit in High Capacity ICPS - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication circuit in a large capacity Information Communication Processing System (ICPS). Particularly, the present invention relates to a serial communication circuit in a microprocessor application system having a bus structure. It relates to a serial communication circuit.

Conventionally, shift registers are used to complicate circuits and to skip several shift registers during clock rise and fall times, making them unsuitable for high-speed data transfers and shifting during data transfers. There was a problem.

According to the present invention, a latch control signal of a decoder is sequentially stored by using a latch connected in parallel to a data bus as much as a burst of data to be transmitted without using a shift register. According to the output through the data output latch buffer, a simple circuit configuration does not occur an error that multiple data at once, high speed serial communication is possible.

Description

High Speed Serial Communication Circuit in High Capacity ICPS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication circuit in a large capacity Information Communication Processing System (ICPS). Particularly, the present invention relates to a serial communication circuit in a microprocessor application system having a bus structure. It relates to a serial communication circuit.

In general, an 8-bit serial communication circuit in high-capacity ICPS, as shown in FIG. 1, uses an input buffer (IB) that receives data to be transmitted from an external system, and serials the data by the number of bits of the corresponding data. Shift registers (SHR1 to SHR7) that receive data from a corresponding input buffer (IB) according to a clock signal applied through a clock terminal CK and shift the data of the corresponding one to the next stage. And a data output latch buffer for temporarily latching and transferring the shifted data applied from the shift registers SHR1 to SHR7 according to the clock signal applied through the clock terminal CK. Buffer; DOLB and data to load or output data to the system through the terminal D of the shift registers SHR1 to SHR7. A clock that generates the clock signal according to the data bus (DB) and the clock generation control signal CKGC and applies it to the clock registers CK of the shift registers SHR1 to SHR7 and the data output latch buffer DOLB. Clock output buffer (CKOB) for controlling the output of the clock generator (CKG), the clock signal applied from the clock generator (CKG) according to the clock output control signal (CKOC), and the clock The clock signal applied from the generator CKG is counted, the clock output control signal CKOC is generated and applied to the clock output buffer CKOB, and the clock generation control signal CKGC is generated to generate the corresponding clock generator ( And a clock counter (CKC) applied to the CKG.

In the large capacity ICPS including the above, the serial communication circuit performs the operation as follows.

First, as data is input through the input buffer IB, each of the shift registers SHR1 to SHR7 receives data from the previous shift register by a clock signal applied from the clock generator CKG through the clock terminal CK. At the same time, it shifts its data to the next stage.

When the shifted data is applied to the data output latch buffer DOLB, the corresponding data output latch buffer DOLB is shifted according to the clock signal applied from the clock generator CKG through the clock terminal CK. Is temporarily stored and output sequentially.

At this time, it is possible to check whether all 8 bits of data have been transmitted by the clock counter CKC, which is determined by counting clock signals applied to the respective shift registers SHR1 to SHR7 from the clock generator CKG. .

After the clock counter CKC counts the number of clock signals, the clock counter CKC generates a clock generation control signal CKGC and applies it to the clock generator CKG, so that the clock generator CKG generates a clock signal. Until the 8-bit data is transferred to each of the shift registers SHR1 to SHR7 and the clock terminal CK of the data output latch buffer DOLB, and generates a clock output control signal CKOC to output the clock. Since it is applied to the buffer CKOB, the clock output buffer CKOB controls the output of the clock signal.

However, by shifting the input data sequentially using the shift registers SHR1 to SHR7, the circuits of the shift registers SHR1 to SHR7 are complicated, and the transfer of data at the rising and falling times of the clock signal is complicated. Since an error may occur in which several shift registers SHR1 to SHR7 are skipped at once, the clock generator CKG must generate a clock signal accurately, which is not suitable for high-speed data transfer and also during data transfer. Because the data is shifted, you may have data that is different from the one you initially set.

As described above, in the related art, a shift register is used, and a circuit is complicated, and several shift registers can be skipped at clock rise and fall times, which is not only suitable for high-speed data transfer, but also shifts during data transfer. There was a problem that can have.

In order to solve the above problems, the present invention provides a high speed serial communication with an external system by using a simple circuit without using a shift register in a microprocessor application system having a bus structure so that an error that causes multiple data passes at once does not occur. It is an object of the present invention to provide a high speed serial communication circuit in a large capacity ICPS.

The present invention for achieving the above object is an input buffer for receiving data to be transmitted from the system, a data bus for loading or outputting data with the system, a clock generator for generating a clock signal in accordance with the clock generation control signal and A clock output buffer for controlling the output of the clock signal applied from the clock generator according to the clock output control signal, a clock signal applied from the clock generator, counting the clock signal, and applying a counting value to generate the clock output control signal In a high-speed serial communication circuit in a high-capacity ICPS having a clock counter applied to a clock output buffer and generating a clock generation control signal and applied to the clock generator, a counting value applied from the clock counter is decoded. A decoder for applying a latch control signal; And a plurality of latches connected in parallel to the data bus as much as the burst of data to be transmitted, thereby sequentially storing the data applied through the data bus and the input buffer in the respective latches, and receiving the latch control signals from the decoder. A latch unit for applying data stored accordingly; And a data output latch buffer for temporarily storing data applied from the latch unit according to a clock signal applied from the clock generator and outputting the data to the serial transmission circuit.

1 is a block diagram showing a serial communication circuit in a typical high-capacity ICPS.

2 is a block diagram illustrating a high speed serial communication circuit in a large capacity ICPS according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

LT: Latch CD: Decoder (Counting Decoder)

DOLB: Data Output Latch Buffer

IB: Input Buffer DB: Data Bus

CKG: Clock Generator

CKOB: Clock Output Buffer

CKC: Clock Counter

In a high-capacity ICPS according to an embodiment of the present invention, the high-speed serial communication circuit may include a latch unit LT including a plurality of latches LT1 to LT8 as shown in FIG. 2 when the data to be transmitted is 8-bit data. Latch, decoder (CD; Counting Decoder), data output latch buffer (DOLB), input buffer (IB), data bus (DB), clock generator (CKG), clock output buffer (CKOB) ) And a clock counter (CKC).

The latch unit LT is connected to the data bus DB in parallel as much as a burst of data to be transmitted according to a latch control signal LC, and records or transmits data to be transmitted. And data applied through the input buffer IB.

The decoder CD generates a latch control signal LC for controlling the output of the latch by decoding the counting value generated by the clock counter CKC.

The data output latch buffer DOLB temporarily stores and outputs the latch output according to a clock signal applied from the clock generator CKG through the clock terminal CK.

Since the input buffer IB, the data bus DB, the clock generator CKG, the clock output buffer CKOB, and the clock counter CKC are the same as in the conventional configuration, description thereof is omitted. .

A high speed serial communication circuit in a large capacity ICPS according to an embodiment of the present invention will be described as follows.

Data to be transmitted through the data bus DB of the system is stored in the latch unit LC through the first D terminal D1 or inputted through the input buffer IB receives the second D terminal D2. When stored in the latch unit LC, the clock generator CKG generates a clock signal and applies the clock signal to the clock counter CKC. The clock counter CKC counts the corresponding clock signal to generate a corresponding counting value. Is applied to the decoder CD, the clock output control signal CKOC is generated and applied to the clock output buffer CKOB, and the clock generation control signal CKGC is generated and applied to the clock generator CKG.

Accordingly, when the decoder CD decodes the counting value applied from the clock counter CKC to generate the latch control signal LC, and applies the generated latch control signal LC to the latch unit LT. The latch unit LT applies the data stored by the latch control signal LC to the input terminal IN of the data output latch buffer DOLB.

Accordingly, the data output latch buffer DOLB finally outputs data applied from the latch unit LT according to a clock signal applied from the clock generation unit CKG through the clock terminal CK.

In other words, each latch LT1 to LT8 of the latch unit LT sequentially stores data to be transmitted through the data bus DB and the input buffer IB of the system, and the clock generator CKG. As the clock counter CKC that counts the clock signal generated by the decoder performs the operation, the decoder CD sequentially applies a latch control signal LC to each latch LT1 to LT8 of the latch unit LT. Therefore, the latches LT1 to LT8 receiving the corresponding latch control signal LC apply the stored data to the input terminal IN of the data output latch buffer DOLB to be output as an output of the serial transmission circuit. do.

In the case of receiving data, as described above, the input data can be received by being sequentially stored in the latches LT1 to LT8 of the latch unit LT.

Therefore, since data stored in each latch LT1 to LT8 of the latch unit LT does not change in the middle of serial transmission, it is very useful when retransmission is needed. It can be minimized and high speed transmission is possible.

As described above, according to the present invention, latches of the decoder are sequentially stored by sequentially storing data to be transmitted through the data bus or the input buffer using a latch connected in parallel to the data bus by the burst of data to be transmitted without using the shift register. By outputting the data through the data output latch buffer according to the signal, high speed serial communication is possible because the simple circuit configuration does not generate an error that multiple data passes at once.

Claims (1)

An input buffer IB receiving data to be transmitted from the system, a data bus DB for loading or outputting data with the system, and a clock generator CKG generating a clock signal according to a clock generation control signal CKGC. And a clock output buffer CKOB for controlling the output of the clock signal applied from the clock generator CKG according to the clock output control signal CKOC, and a clock signal applied from the clock generator CKG. A clock counter that applies a counting value, generates a corresponding clock output control signal CKOC, applies it to the corresponding clock output buffer CKOB, generates a corresponding clock generation control signal CKGC, and applies it to the corresponding clock generator CKG. In a high-speed serial communication circuit in a large capacity ICPS having a CKC, a decoder CD for decoding a counting value applied from the clock counter CKC and applying a corresponding latch control signal LC. .; A plurality of latches LT1 to LT8 are connected to the data bus DB in parallel as much as the burst of data to be transmitted to sequentially apply data applied through the data bus DB and the input buffer IB. A latch unit LT stored in the latches LT1 to LT8 and applying stored data in accordance with a latch control signal LC applied from the decoder CD; And a data output latch buffer DOLB that temporarily stores data applied from the latch unit LT according to a clock signal applied from the clock generator CKG and outputs the data to the serial transmission circuit. High speed serial communication circuit in large capacity ICPS.