KR100200490B1 - Data interface apparatus - Google Patents

Abstract

The present invention discloses a data interface device. The apparatus is characterized by converting 2 (n-x + 1) bits of parallel data into serial data or between 2n bits between a first signal processor for inputting / outputting parallel data and a second signal processor for inputting / outputting serial data. A data interface device for converting serial data into parallel data of 2 (n-x + 1) bits, comprising: responding to a first clocking control signal with 2n bits of serial data from the second signal processor in response to a bit clock signal Inputs the upper n bits and the lower n bits of data of the 2n bits of data by shifting and shifts and discards the x-1 bit data of the x bits of data having the same value among the upper n bits and the lower n bits of data and shifts the upper n bits. 2 (n-x + 1) bit data of -x + 1 bits and lower n-x + 1 bits are stored in response to the first load control signal and in parallel to the first signal processor in response to the first control signal. Serial / parallel conversions for output However, in response to the second control signal, parallel data of 2 (n-x + 1) bits from the first signal processor is input, and 2 (n-x + 1) bit data in response to the second load control signal. And parallel / serial conversion means for shifting parallel data of 2 (n-x + 1) bits and outputting them in series to the second signal processor in response to a second shifting control signal, and the word clock signal and And a control means for inputting a channel clock signal to generate first and second load control signals and the first and second shifting control signals.

Description

Data interface device

The present invention relates to a data interface device, and more particularly, to a data interface device capable of converting data in parallel or in series with a small number of registers.

In general, an interface circuit is used when parallel data is converted into serial data or serial data is converted into parallel data.

1 is a diagram illustrating a connection relationship between a general data interface device and an emulation board. Reference numeral 10 denotes an emulation board and 12 an interface device.

The emulation board 10 shown in FIG. 1 includes a digital signal processor (DSP). In addition, among the peripheral devices of the emulation board, there is a digital audio interface unit (DAIU) for interfacing digital audio data, and the DAIU is a kind of data interface unit 12, which is an audio compact disk (CD) application. Applications such as a moving picture expert group (MPEG) decoder for a CD-DSP for video or a video CD application can be external.

FIG. 2 is for explaining the necessity of the interface device shown in FIG. 1 and includes a first signal processor 20, an interface device 22, and a second signal processor 24.

The first signal processor 20 shown in FIG. 2 is a DSP core, and the second signal processor 24 is, for example, a digital-to-analog converter (DAC). It is assumed that the first signal processor 20 inputs and outputs only parallel data, and the second signal processor 24 inputs and outputs only serial data. At this time, in order for the second signal processing unit 24 to process the data of the first signal processing unit 20, the parallel data must be converted into serial data in the interface device 22.

FIG. 3 is a block diagram of a register representing a data receiving and converting operation of a conventional interface device. FIG. 3a shows 48 registers rxdr for storing shifted data, and FIG. 3b shows input data din. Shifting 48 registers (rxsr), ext represents a register for outputting the data stored in the register (rxdr) to the outside.

FIG. 4 is a block diagram of a register for performing data transmission and conversion operations of a conventional interface device. EXT is a register for storing serial data input from an external device. FIG. 4A is for loading and storing data stored in EXT. 4b shows registers txsr for shifting data.

Conventional data interface devices are used for audio-CD applications (48-bit mode) among audio-CD applications and video-CD applications using different shifting clocks, respectively, as shown in the registers shown in FIGS. 3A-4B. Up to 48 registers are required.

However, since the bit data of the 47th bit to the 39th bit and the 23rd bit to the 15th bit of the 48 bit data are all 0 or all 1 data, it is not necessary to store all of the 48 bit data. The data interface device uses a 48-bit register to store all the 48-bit data, there is a problem that a lot of registers are wasted.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data interface device capable of performing an interface function as a small number of registers in order to solve the above conventional problems.

A data interface device of the present invention for achieving the above object is a parallel of the 2 (n-x + 1) bit between the first signal processor for input / output parallel data and the second signal processor for input / output serial data A data interface device for converting data into serial data or converting 2n bits of serial data into 2 (n-x + 1) bits of parallel data, comprising: 2n bits from the second signal processor in response to a bit clock signal. Shifting serial data in response to a first shifting control signal to input upper n bits and lower n bits of data of 2n bits and shifting to have x (xn) having the same value among the upper n bits and lower n bits of data. Discards x-1 bit data among the bit data and stores 2 (n-x + 1) bit data of the upper n-x + 1 bit and the lower n-x + 1 bit in response to the first load control signal. Phase in response to a control signal Serial / parallel conversion means for outputting in parallel to a first signal processor, and in response to a second control signal, 2 (n-x + 1) bits of parallel data from the first signal processor are input and second load control is performed. 2 (n-x + 1) -bit data is stored in response to the signal, 2 (n-x + 1) -bit parallel data is shifted in response to the second shifting control signal, and output in series to the second signal processor. Parallel / serial conversion means, and control means for inputting the word clock signal and the channel clock signal to generate first and second load control signals and the first and second shifting control signals.

1 shows a connection relationship with an emulation board of a general interface device.

2 is for explaining the necessity of the interface device shown in FIG.

3A and 3B show a configuration of a register for performing data reception and conversion operations of a conventional interface device.

44A and 44B show configurations of registers for performing data transmission and conversion operations of a conventional interface device.

5 is a block diagram of a data interface device according to the present invention.

6 is a block diagram of the control unit shown in FIG.

7 is a configuration diagram of the serial-to-parallel converter shown in FIG.

8 is a configuration diagram of the parallel-to-serial conversion unit shown in FIG.

9a-e are timing diagrams of respective terminals shown in FIG. 5 in an audio-CD application.

10A-C are timing diagrams of the third counter shown in FIG.

11a-d are timing diagrams of each terminal shown in FIG. 5 in a video-CD application.

12A-D are timing diagrams of shifting control signals and shifting counting signals in an audio-CD application.

13A-C are timing diagrams of shifting control signals and shifting counting signals in a video-CD application.

14A-E are timing diagrams for explaining the load signal.

Hereinafter, the configuration and operation of a data interface device according to the present invention will be described with reference to the accompanying drawings.

5 is a block diagram of a data interface device according to the present invention, and is composed of a serial-to-parallel converter 32, a controller 34, and a parallel-to-parallel converter 36.

FIG. 6 is a block diagram showing the configuration of the control unit 34 shown in FIG. 5 and includes a logic unit 40, a first counter 42, a second counter 44, and a third counter 46. It is.

The control unit shown in FIG. 6 inputs the channel clock signal CC and the word clock signal WC to input the logic unit 40, the first counter 42, the second counter 44, and the third counter 46. ) Generates first and second load control signals C _L1 and C _L2 , and first and second shifting control signals C _CE1 and C _CE2 .

FIG. 7 is a block diagram showing the configuration of the serial-to-parallel converter 32 shown in FIG. 5, wherein the external registers (EXT) 48, the receive data register 50, the upper receive shift register 52, and the lower receive. The shift register 54 and the multiplexer 56 are comprised.

The shift register 54 shown in FIG. 7 of the serial-to-parallel converter 32 shown in FIG. 5 is output from the second signal processor 24 shown in FIG. 2 and is input through the input terminal IN1. The shifting operation is performed when the shifting control signal C _CE1 is input to the controller 34 in synchronization with the falling edge of the bit clock CK. The shifted data stored in the reception shift register 54 is stored in the reception data register 52 in response to the loading signal C _L1 output from the controller 34. The data stored in the reception data register 52 is output to the first signal processor 20 through the data bus 38 through the external register 50 in response to the control signal C1 input through the input terminal IN2. do.

8 is a configuration diagram of the parallel-to-serial conversion unit 36 shown in FIG. 5, and is composed of an external register (EXT) 60, a transmission data register 62, and a transmission shift register 64. As shown in FIG. The external register 60 is the same register as that of the external register 48 in FIG. 7 and only shows the numbers differently.

The parallel-to-serial conversion unit 36 shown in FIG. 5 transmits the parallel data PD stored in the external register 60 in response to the control signal C2 applied through the input terminal IN3. Save as. Data stored in the transmission data register 62 is stored in the transmission shift register 64 in response to the loading signal C _L2 generated from the control unit 34.

Data stored in the transmission shift register 64 is shifted when the shifting control signal C _CE2 is applied from the control unit 34 in synchronization with the rising edge of the bit clock CK. The shifted serial data is output from the transmission shift register 64 to the second signal processing section 24 shown in FIG. 2 through the output terminal OUT.

The following description will be made with reference to the timing diagram to which the operation of the control part 34 shown in FIG. 5 is attached.

9a to 9e are timing diagrams of the respective terminals shown in FIG. 5 in an audio-CD application, in which FIG. 9a is a bit clock, FIG. 9B is a channel clock (CC), and FIG. 9c is a word clock (or left and right discrimination). Fig. 9d shows serial data input to the serial-to-parallel converter 32, and Fig. 9e shows timing charts for the serial data output from the parallel-to-parallel converter 36, respectively.

10A and 10B are timing diagrams of output signals of the third counter 46 shown in FIG. 6A, and FIG. 10A is a counting enable signal, and FIG. 10B is a timing diagram of the first shifting control signal. 10c shows timing charts of the second shifting control signal, respectively.

11A to 11D are timing diagrams of respective terminals shown in FIG. 5 in a video-CD application (32-bit mode). FIG. 11A is a bit clock, FIG. 11B is a word clock, and FIG. 11C is a parallel-parallel converter. The serial data input to (32) and FIG. 11d show timing charts of the serial data output from the parallel-to-serial conversion section 36, respectively.

12A to 12D are timing diagrams of signals input to a control unit 34 for explaining a shift control signal in an audio-CD application (48-bit mode). FIG. 12A is a bit clock, FIG. 12B is a word clock, FIG. 12C shows a channel clock and FIG. 12D shows a timing diagram of the shifting counting signal.

13a to 13c are timing diagrams of signals input to the control unit 34 for explaining the shift control signal in a video-CD application. FIG. 13a is a bit clock, FIG. 13b is a word clock, and FIG. 13c is a shifting counting signal. Each shows a timing diagram.

Figures 14a-14e are timing diagrams for explaining the loading signal. Figure 14a is a bit clock, Figure 14b is a shifting counting signal, Figure 14c is a clock signal, Figure 14d is a shifting counting signal of a clock, and Figure 14e is a In the case of the 48-bit mode and the 32-bit mode, the timing diagrams of the loading signals are shown.

In the control unit 34 shown in FIG. 6, the first counter 42 counts the bit clock shown in FIG. 9A, the second counter 44 counts the clock, and the third counter 46 has 4 bits. As a counter, in the case of an audio-CD application, a counting operation is performed when the channel clock shown in FIG. 9C is at a low level. As shown in FIG. 10A, when the value of the third counter 46 is 0, 9, 10, 11, and 12, the first and second shifting control signals shown in FIGS. 10B and 10C are respectively controlled. Output from the 34 to the parallel-to-serial conversion section 36.

In the case of a video-CD application, referring to FIGS. 11a-11d, it can be seen that transmission and reception are possible in 32-bit registers.

The shifting counting signals shown in FIGS. 12D and 13C, respectively, are divided into a bit clock and a clock, and will be described below.

In the case of the audio-CD in the bit clock, if the word clock shown in FIG. 12B and the channel clock shown in FIG. 12C are at a high level, the value of the third counter 46 is increased by one, and in the case of video-CD, the word If the clock is at a low level, the value of the third counter 46 is increased by one.

In the case of audio-CD in the clock, when the value of the third counter 46 is 12, the value of the third counter 46 is increased by one, and in the case of the video-CD, the counter value is 16 when the counter value is 16. Increment by 1

As described above, since the data interface device according to the present invention requires only 32 S4 = 128 registers in total, there is an effect that 64 registers can be reduced compared to the number of conventional registers, that is, 48 S4 = 192. .

Claims (3)

The 2 (n-x + 1) bits of parallel data is converted into serial data or the 2n bits of serial data between the first signal processor for inputting / outputting parallel data and the second signal processor for inputting / outputting serial data. A data interface device for converting 2 (n-x + 1) bits into parallel data, comprising: shifting 2n bits of serial data from the second signal processor in response to a first shifting control signal in response to a bit clock signal Input and shift the upper n bits and lower n bits of data of 2n bits to discard x-1 bits of x-bit data having the same value among the upper and lower n bits of data, and then discard upper n-x + 2 (n-x + 1) bit data of one bit and the lower n-x + 1 bits are stored in response to a first load control signal and output in parallel to the first signal processor in response to a first control signal. Serial / parallel conversion means; In response to a second control signal, 2 (n-x + 1) bits of parallel data from the first signal processor are input, and 2 (n-x + 1) bits of data are stored in response to a second load control signal. Parallel / serial conversion means for shifting 2 (n-x + 1) bits of parallel data in series to the second signal processor in response to a second shifting control signal; And control means for inputting the word clock signal and the channel clock signal to generate first and second load control signals and the first and second shifting control signals. The upper and lower x bits according to claim 1, wherein the serial / parallel conversion means has the same data among the upper n bits and lower n bits of serial data input through the first output terminal in response to the shifting control signal. A first register for storing 2 (n-x + 1) -bit data by discarding x-1 bit data of the data and shifting n-x + 1 bit data; A second register for storing 2 (n-x + 1) bit parallel data stored in the first register in response to the first load control signal; And a third register for storing data stored in the second register in response to the first control signal. 3. The apparatus of claim 2, wherein the parallel / serial conversion means comprises: a fourth register for storing 2 (n-x + 1) bit data stored in the third register in response to the second control signal; And a fifth register for storing data stored in the fourth register in response to the second load control signal and shifting and outputting 2 (n-x + 1) bit data in response to the second shifting control signal. A data interface device, characterized in that.