KR960002782B1 - Method of manufacturing the stacked capacitor for a semiconductor memory device - Google Patents
Method of manufacturing the stacked capacitor for a semiconductor memory device Download PDFInfo
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- KR960002782B1 KR960002782B1 KR1019920009726A KR920009726A KR960002782B1 KR 960002782 B1 KR960002782 B1 KR 960002782B1 KR 1019920009726 A KR1019920009726 A KR 1019920009726A KR 920009726 A KR920009726 A KR 920009726A KR 960002782 B1 KR960002782 B1 KR 960002782B1
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- charge storage
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- 239000003990 capacitor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000003860 storage Methods 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000009833 condensation Methods 0.000 claims 1
- 230000005494 condensation Effects 0.000 claims 1
- 239000011229 interlayer Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
제1도는 종래의 DRAM 셀 단면도.1 is a cross-sectional view of a conventional DRAM cell.
제2도는 본 발명에 따른 DRAM 셀 제조 공정도.2 is a DRAM cell manufacturing process diagram according to the present invention.
제3도는 본 발명에 따른 DRAM 셀 평면도.3 is a plan view of a DRAM cell according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
201 : 실리콘 기판 202 : 필드 산화막201: silicon substrate 202: field oxide film
203 : N+활성영역 204 : 워드선203: N + active region 204: word line
205,206,207 : 층간절연막 208 : 비트선205,206,207 Interlayer insulating film 208 Bit line
209 : 전하저장전극 210 : 유전막209: charge storage electrode 210: dielectric film
211 : 플레이트 전극 212 : 금속배선211: plate electrode 212: metal wiring
213a,213b : 제1 및 제2감광막 패턴213a and 213b: first and second photoresist film patterns
본 발명은 반도체 메모리 소자의 캐패시터 제조 방법에 관한 것으로, 특히 적층 (Stack)캐패시터의 구조를 이용하여 큰 저장 캐패시터 면적을 갖게 함으로써 DRAM의 단위 셀 면적을 작게 할 수 있는 적층 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method of manufacturing a stacked capacitor capable of reducing a unit cell area of a DRAM by having a large storage capacitor area using a structure of a stacked capacitor.
일반적으로, DRAM 셀은 잘 알려진 바와 같이 한 개의 트랜지스터와 한 개의 캐패시터로 이루어져 있다. 셀 외부의 전극으로는 워드선, 비트선, 그리고 캐패시터 플레이트(plate)전극으로 구성되어 있으며 DRAM의 집적도는 날로 증가하여 최근에는 64M DRAM의 시제품도 발표되고 있는 실정이다.Generally, a DRAM cell consists of one transistor and one capacitor, as is well known. The electrode outside the cell is composed of a word line, a bit line, and a capacitor plate electrode. As the density of DRAM increases, prototypes of 64M DRAM have recently been announced.
제1도는 일본의 히다치(Hitachi)에서 발표된 DRAM 셀 단면도로서, 1은 실리콘 기판, 2는 필드 산화막, 3은 N+활성영역, 4는 워드선, 5,6,7은 층간절연막, 8은 비트선, 9는 캐패시터의 전하저장전극, 10은 캐패시터의 유전막, 11은 캐패시터의 플레이트 전극, 12는 금속배선을 각각 나타낸다.1 is a cross-sectional view of a DRAM cell published by Hitachi, Japan, where 1 is a silicon substrate, 2 is a field oxide film, 3 is an N + active region, 4 is a word line, 5, 6, 7 is an interlayer insulating film, and 8 is The bit line, 9 represents the charge storage electrode of the capacitor, 10 represents the dielectric film of the capacitor, 11 represents the plate electrode of the capacitor, and 12 represents metal wiring.
상기 제1도에 도시된 바와 같이 적층(Stack)캐패시터의 구조의 DRAM은 비트선(8)을 전하저장전극(9)의 형성 공정 이전에 형성하는 구조로써 비트선(8)의 접촉 영역까지 캐패시터 면적을 크게 한 것이다.As shown in FIG. 1, a DRAM having a stacked capacitor has a structure in which the bit line 8 is formed before the formation process of the charge storage electrode 9, and the capacitor reaches the contact region of the bit line 8. The area is enlarged.
그러나, 디자인 규칙이 작아지면서 셀 면적도 작아져 상기 제1도의 셀 구조에서는 원하는 캐패시터 면적을 확보하는데 있어서 한계에 도달하는 문제점이 있다.However, as the design rule becomes smaller and the cell area becomes smaller, the cell structure of FIG. 1 has a problem of reaching a limit in securing a desired capacitor area.
따라서, 상기 문제점을 해결하기 위한 본 발명은 기존의 공정 기술을 그대로 이용하면서 캐패시터 면적을 대폭 증가시켜 성능이 우수한 고집적 DRAM 셀을 제작할 수 있는 반도체 메모리 소자의 적층 캐패시터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a stacked capacitor of a semiconductor memory device capable of fabricating a highly integrated DRAM cell having excellent performance by greatly increasing the capacitor area while using existing process technology. .
상기 목적을 달성하기 위하여 본 발명은, 반도체 메모리 소자의 적층 캐패시터 제조 방법에 있어서, 일반적인 DRAM 제조 공정으로 워드선과 비트선을 형성하고 캐패시터의 전하저장전극 콘택을 위해 활성영역을 개방하고 전하저장전극용 다결정실리콘상을 증착하는 제1공정, 상기 제1공정 후에 상기 다결정실리콘상에 전하저장전극 마스크인 제1감광막 패턴을 형성하고, 상기 제1감광막 패턴을 식각장벽으로 상기 다결정실리콘의 전체두께중 소정두께를 식각하는 제2공정, 상기 제2공정 후에 상기 제1감광막 패턴을 제거하고, 상기 제1감광막 패턴과 동일한 형상의 제2감광막 패턴을 제1감광막 패턴 위치에서 소정 길이 옆으로 이동시켜 형성한 후, 상기 제2감광막 패턴을 식각장벽으로 상기 다결정실리콘 식각시 남은 나머지 두께의 상기 다결정실리콘을 식각하는 제3공정, 및 상기 제3공정 후에 상기 제2감광막 패턴을 제거하고 상기 다결정실리콘상에 유전막을 증착하고 전체구조 상부에 플레이트 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a stacked capacitor of a semiconductor memory device, forming a word line and a bit line in a general DRAM manufacturing process, open the active region for the charge storage electrode contact of the capacitor, A first process of depositing a polysilicon phase, and after the first process, a first photoresist pattern, which is a charge storage electrode mask, is formed on the polysilicon, and the first photoresist pattern is an etch barrier, and the predetermined thickness of the polysilicon is determined. After the second process of etching the thickness and the second process, the first photoresist pattern is removed, and the second photoresist pattern having the same shape as the first photoresist pattern is moved by a predetermined length from the position of the first photoresist pattern. Thereafter, the second photoresist pattern is used as an etch barrier to the polysilicon of the remaining thickness when the polysilicon is etched. SIR is characterized in that it comprises a third step, and further comprising: after the third step of removing the second photosensitive film pattern, and depositing a dielectric layer on said polycrystalline silicon and forming a plate electrode on the entire upper structure.
이하, 첨부된 도면 제2도 및 제3도를 참조하여 본 발명에 따른 일실시예를 자세히 설명하면 다음과 같다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIGS. 2 and 3 of the accompanying drawings.
제2도는 본 발명에 따른 DRAM 셀 제조 공정도로서, 도면에서 201은 실리콘 기판, 202는 필드 산화막, 203은 N+활성영역, 204는 워드선, 205,206,207은 층간절연막, 208은 비트선, 209는 전하저장전극용폴리실리콘막, 210은 유전막, 211은 플레이트 전극, 212는 금속배선, 213a, 213b은 제1및 제2감광막 패턴을 각각 나타낸다.2 is a process diagram of a DRAM cell manufacturing according to the present invention, where 201 is a silicon substrate, 202 is a field oxide film, 203 is an N + active region, 204 is a word line, 205, 206, 207 is an interlayer insulating film, 208 is a bit line, and 209 is a charge The polysilicon film for the storage electrode, 210 is a dielectric film, 211 is a plate electrode, 212 is a metal wiring, and 213a and 213b are first and second photoresist film patterns, respectively.
먼저, 제2a도와 같이 일반적인 DRAM 공정으로 워드선(204)과 비트선 (208)을 형성하고 전하저장전극(209)의 콘택을 위해 N+활성영역(203)을 개방하고 전하저장전극용 다결정실리콘(209)으로 증착한 다음, 전하저장전극 마스크인 제1감광막 패턴(213a)을 형성한다. 이어서, 제1감광막 패턴(213a)을 식각장벽으로 하여 상기 다결정실리콘(209)을 1/2두께 정도만 식각해 낸다. 이때 전하저장전극(209)사이의 최소 간격은 일반적으로 디자인 룰(λ)에 의해 결정된다.First, as shown in FIG. 2A, the word line 204 and the bit line 208 are formed by a general DRAM process, the N + active region 203 is opened for the contact of the charge storage electrode 209, and the polysilicon for the charge storage electrode is formed. After deposition at 209, the first photoresist pattern 213a serving as the charge storage electrode mask is formed. Subsequently, only about 1/2 the thickness of the polysilicon 209 is etched using the first photoresist pattern 213a as an etch barrier. In this case, the minimum distance between the charge storage electrodes 209 is generally determined by the design rule λ.
이어서, 제2b도와 같이 상기 제1감광막 패턴(213a)을 제거하고, 상기 제1감광막 패턴과 동일한 형상의 제2감광막 패턴(213b)을 제1감광막 패턴(213a)위치에서 일정 길이 x(0＜x＜λ)만큼 옆으로 이동시켜 형성하고, 상기 제2감광막 패턴(213b)을 식각장벽으로 상기 다결정실리큰(209)식각시 남은 나머지 1/2두께의 상기 다결정실리콘(209)을 식각해 낸다. 이렇게 하면 종래의 경우와 달리 전하저장전극간의 간격은 디자인 룰(λ)보다 작게 된다. 즉, 디자인 룰의 1/2이 되어 전하저장전극의 면적을 크게 할 수 있다.Subsequently, as shown in FIG. 2B, the first photoresist pattern 213a is removed, and the second photoresist pattern 213b having the same shape as the first photoresist pattern is disposed at a predetermined length x (0 <) at the position of the first photoresist pattern 213a. It is formed by moving laterally by x < lambda), and the polysilicon 209 of the remaining half thickness is etched by etching the polycrystalline silicon 209 using the second photoresist pattern 213b as an etch barrier. . In this case, unlike the conventional case, the distance between the charge storage electrodes is smaller than the design rule λ. In other words, it becomes 1/2 of the design rule to increase the area of the charge storage electrode.
끝으로, 상기 제2감광막 패턴(213b)을 제거하고, 캐패시터 유전막(210)을 증착하고 캐패시터 플레이트 전극(211)을 형성을 위한 다결정실리콘을 증착한 다음에 층간절연막(207)을 형성하고, 금속배선(212)을 형성 한다.Finally, the second photoresist layer pattern 213b is removed, the capacitor dielectric layer 210 is deposited, and polycrystalline silicon is deposited to form the capacitor plate electrode 211, and then the interlayer insulating layer 207 is formed, and the metal The wiring 212 is formed.
제3도는 본 발명에 따른 DRAM 셀 평면도로서, 본 발명에 따른 적층 캐패시터 제조 방법의 작용 효과를 제3도를 통하여 구체적으로 살펴보면 다음과 같다.FIG. 3 is a plan view of a DRAM cell according to the present invention. The operation and effect of the multilayer capacitor manufacturing method according to the present invention will be described in detail with reference to FIG.
일반적으로 DRAM 셀의 면적은 2λ×4λ=8λ2(λ :디자인 룰)이며 여기서 캐패시터가 차지하는 면적은 셀 면적에서 가로와 세로에서 각각 λ만큼만을 뺀 나머지 부분이 된다. 즉, λ×3λ=3λ2가 된다. 그러나 본 발명의 셀 구조에서 만약, 상기 워드선 (204)방향으로 λ/2만큼 전하저장전극 마스크를 이동시켰다면 캐패시터 면적은 1.5λ×3λ=4.5λ2가 되고, 비트선(208)방향으로 전하저장전극 마스크를 이동시켰다면 캐패시터 면적을 λ×3.5λ=3.5λ2가 된다. 또한, 워드선(204) 및 비트선(208)두 방향으로 모두 이동시키면 캐패시터 면적은 (1.5λ×3.5λ)-(2×0.5λ×0.5λ)=4.75λ2가 되어 종래의 셀 구조보다 약 60% 정도의 캐패시터 면적을 증가시킬 수 있다. 그리고, 상기 마스크 이동에 의하여 상기 전하저장전극(209)의 자체에서 단차가 발생하기 때문에 단차에 의한 캐패시터 면적의 증가 또한 기대할 수 있다.In general, the area of a DRAM cell is 2λ × 4λ = 8λ 2 (λ: design rule), and the area occupied by the capacitor is the remaining portion of the cell area minus only λ in width and length. That is, λ × 3λ = 3λ 2 . However, in the cell structure of the present invention, if the charge storage electrode mask is moved by [lambda] / 2 toward the word line 204, the capacitor area is 1.5 lambda x 3 lambda = 4.5 lambda 2 and the charge in the bit line 208 direction. If the storage electrode mask is moved, the capacitor area is λ × 3.5λ = 3.5λ 2 . Also, if the word line 204 and the bit line 208 are moved in both directions, the capacitor area becomes (1.5λ × 3.5λ) − (2 × 0.5λ × 0.5λ) = 4.75λ 2 , which is higher than that of the conventional cell structure. The capacitor area can be increased by about 60%. In addition, since a step occurs in the charge storage electrode 209 by the mask movement, an increase in the capacitor area due to the step may be expected.
따라서, 상기 본 발명의 실시예에 있어서 종래와 동일한 마스크로 전하저장전극의 크기를 워드선, 비트선 방향으로 확장하여 축적 용량을 증가시킬 수 있을 뿐만 아니라, 단차에 의한 축적 용량증가를 얻을 수 있는 효과가 있다.Therefore, in the embodiment of the present invention, the size of the charge storage electrode can be expanded in the direction of the word line and the bit line with the same mask as in the related art, and the storage capacity can be increased, and the storage capacity can be increased by the step. It works.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019920009726A KR960002782B1 (en) | 1992-06-05 | 1992-06-05 | Method of manufacturing the stacked capacitor for a semiconductor memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019920009726A KR960002782B1 (en) | 1992-06-05 | 1992-06-05 | Method of manufacturing the stacked capacitor for a semiconductor memory device |
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| Publication Number | Publication Date |
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| KR940001413A KR940001413A (en) | 1994-01-11 |
| KR960002782B1 true KR960002782B1 (en) | 1996-02-26 |
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