KR940001413A - Manufacturing method of stacked capacitor of semiconductor memory device - Google Patents

Manufacturing method of stacked capacitor of semiconductor memory device Download PDF

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Publication number
KR940001413A
KR940001413A KR1019920009726A KR920009726A KR940001413A KR 940001413 A KR940001413 A KR 940001413A KR 1019920009726 A KR1019920009726 A KR 1019920009726A KR 920009726 A KR920009726 A KR 920009726A KR 940001413 A KR940001413 A KR 940001413A
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KR
South Korea
Prior art keywords
polycrystalline silicon
memory device
depositing
semiconductor memory
manufacturing
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Application number
KR1019920009726A
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Korean (ko)
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KR960002782B1 (en
Inventor
고요환
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019920009726A priority Critical patent/KR960002782B1/en
Publication of KR940001413A publication Critical patent/KR940001413A/en
Application granted granted Critical
Publication of KR960002782B1 publication Critical patent/KR960002782B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 메모리 소자의 적층 캐패시터에 관한 것으로, 종래와 동일한 마스크로 저장 노우드의 크기를 워드선, 비트 선 방향으로 확장 하여 축적 용량을 증가 시킬수 있을 룬만 아니라, 단차에 의한 축적용량 증가를 실현하여, 적층(Stack)캐패시터 구조의 큰 저장 캐패시터 면적을 갖게 함으로써 DRAM의 단위셀 면적을 작게 할 수 있는 적층 캐패시터 셀 제조방법에 관한것이다.The present invention relates to a stacked capacitor of a semiconductor memory device, and not only can increase the storage capacity by expanding the storage norm in the word line and bit line direction with the same mask as in the related art, but also realizes an increase in the storage capacity by a step. Accordingly, the present invention relates to a method of manufacturing a stacked capacitor cell capable of reducing a unit cell area of a DRAM by having a large storage capacitor area of a stacked capacitor structure.

Description

반도체 메모리 소자의 적층 캐패시터 제조 방법Manufacturing method of stacked capacitor of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 본 발명에 따른 DRAM 셀 공정도.DRAM cell process diagram according to the invention of FIG.

Claims (5)

반도체 메모리 소자의 적층 캐패시터 제조 방법에 있어서, 일반적 인 DRAM공정으로 워드선(4)과 비트선(8)을 형성하고 저장 노드부 (9)와의 접촉위해 N+활성 영역(3)을 개방하고 저장 노드부(9)전극을 다결정 실리콘으로 증착 하여 감광막(13)을 증착하는 제1공정, 상기 제1공정 후에 상기 저장 노드부(9)를 마스크 패턴 하여 상기 증착한 저장 노드부(9)의 다결정 실리콘 일부률 식각하는 제2공정. 상기 제2공정후에 저장 노드부(9) 마스크를 이용하여 일정길이로 옆으로 이동시켜, 상기 다결정 실리콘식각시 남은 나머지 두께의 상기 다결정 실리콘을 식각하는 제3공정, 및 상기 제3공정 후에 유전체인 캐패시터 절연막(10)을 증착하고 캐패시터 판(11)형성을 위해 다결정 실리콘을 증착한 다음에 층간 절연막(7) 금속(12)을 순서적 으로 증착하여 상기 금속(12)을 패턴하여 식각하는 제4공정을 구비 하는 것을 특징으로 하는 반도체 메모리 소자의 적층 캐패시터 제조방법.In the method of manufacturing a stacked capacitor of a semiconductor memory device, the word line 4 and the bit line 8 are formed by a general DRAM process, and the N + active region 3 is opened and stored for contact with the storage node unit 9. The first step of depositing the photoresist layer 13 by depositing the electrode part 9 with polycrystalline silicon, and the polycrystalline crystal of the deposited storage node part 9 by masking the storage node part 9 after the first step. The second process of etching the partial fraction of silicon. After the second process, by using the storage node 9 mask to move sideways at a predetermined length, the third process of etching the polycrystalline silicon of the remaining thickness during the polycrystalline silicon etching, and the dielectric after the third process A fourth layer for patterning and etching the metal 12 by depositing a capacitor insulating film 10 and depositing polycrystalline silicon to form a capacitor plate 11, and then sequentially depositing an interlayer insulating film 7 and a metal 12. A method of manufacturing a stacked capacitor of a semiconductor memory device, characterized in that it comprises a step. 제1항에 있어서, 상기 제2공정의 다결정 실리콘 식각두께는 상기 증착한 다결정 실리콘의 1/2인 것을 특징으로 하는 반도체 메모리 소자의 적층 캐패시터 제조방법.The method of claim 1, wherein the polycrystalline silicon etching thickness of the second process is 1/2 of the deposited polycrystalline silicon. 제1항에 있어서, 상기 제3공정의 마스크 이동 거리는 디자인 규칙 λ의 1/2인 것을 특징으로 하는 반도체 메모리 소자의 적층 캐패시터 제조 방법.The method of claim 1, wherein the mask movement distance of the third step is 1/2 of the design rule?. 제3항에 있어서, 마스크이동 방향은 워드선(4)및 비트선(8)방향중 어느하나인 것을 특징으로 하는 반도체 메모리 소자의 적층 캐패시터 제조방법.4. The method of claim 3, wherein the mask movement direction is any one of word line (4) and bit line (8) directions. 제3항에 있어서. 마스크이동 방향은 상기 워드선(4) 및 비트선(8)의 두방향인 것을 특징으로 하는 반도체 메모리 소자의 적층 캐패시터 제조 방법.The method of claim 3. The mask movement direction is a two-way direction of the word line (4) and the bit line (8), characterized in that the manufacturing method of the stacked capacitor of the semiconductor memory device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920009726A 1992-06-05 1992-06-05 Method of manufacturing the stacked capacitor for a semiconductor memory device KR960002782B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920009726A KR960002782B1 (en) 1992-06-05 1992-06-05 Method of manufacturing the stacked capacitor for a semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920009726A KR960002782B1 (en) 1992-06-05 1992-06-05 Method of manufacturing the stacked capacitor for a semiconductor memory device

Publications (2)

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KR940001413A true KR940001413A (en) 1994-01-11
KR960002782B1 KR960002782B1 (en) 1996-02-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102376751B1 (en) * 2021-08-06 2022-03-21 이경철 Waste catcher grinding system with noise and dust reduction functions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102376751B1 (en) * 2021-08-06 2022-03-21 이경철 Waste catcher grinding system with noise and dust reduction functions

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