KR960002702A - MOSFET and manufacturing method - Google Patents

Abstract

The present invention relates to a MOSFET and a method of manufacturing the same, and solves the problem caused by forming a P well on the semiconductor substrate, forming a device isolation oxide film, a gate oxide film and a gate electrode in the prior art, and then forming a MOSFET in an LDD structure. In order to form a device isolation oxide film, a gate oxide film, and a gate electrode on the semiconductor substrate, a P well is formed only partially between the gate electrode and the device isolation oxide film, and then an insulating film spacer is formed on the sidewall of the gate electrode. By injecting a high concentration of impurity ions using a spacer as a mask, a MOSFET is manufactured to have a constant slope in a high concentration impurity region and an inverted N-channel region between a source and a drain, thereby simplifying the process, device isolation, ESD, threshold voltage, Leakage current, short channel effect and hot carrier characteristics can be improved. In other words, it is a technology capable of improving reliability and productivity of semiconductor devices and enabling high integration of semiconductor devices.

Description

MOSFET and manufacturing method

Figure 2C is a cross-sectional view showing a MOSFET manufacturing process according to an embodiment of the present invention.

Claims (5)

In the MOSFET, a channel stop, a device isolation oxide film, a gate oxide film, and a gate electrode are provided at a predetermined portion of the semiconductor substrate, a P well is provided between the gate electrode and the device isolation oxide film, and an insulating film spacer is formed on the sidewall of the gate electrode. And a high concentration impurity region between the insulating film spacer and the device isolation oxide film. The MOSFET according to claim 1, wherein the high concentration impurity region is provided at a predetermined slope. In the method of manufacturing a MOSFET, a process for forming a channel stop, a device isolation oxide film, a gate oxide film and a gate electrode on the semiconductor substrate, and implanting impurity ions between the gate electrode and the device isolation oxide film using the gate electrode as a mask, And forming a well insulating layer on the sidewalls of the gate electrode, and implanting a high concentration of impurity ions using the insulating layer spacer as a mark to form a small concentration of impurity region. The method of claim 3, wherein the P well is partially formed only between the gate electrode and the device isolation oxide layer. The method of claim 3, wherein the high concentration impurity region is formed to have a predetermined slope. ※ Note: The disclosure is based on the initial application.