KR960001471Y1 - Seramic package - Google Patents

Seramic package Download PDF

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Publication number
KR960001471Y1
KR960001471Y1 KR2019890019728U KR890019728U KR960001471Y1 KR 960001471 Y1 KR960001471 Y1 KR 960001471Y1 KR 2019890019728 U KR2019890019728 U KR 2019890019728U KR 890019728 U KR890019728 U KR 890019728U KR 960001471 Y1 KR960001471 Y1 KR 960001471Y1
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South Korea
Prior art keywords
ceramic package
package
seramic
present
edge
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KR2019890019728U
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Korean (ko)
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KR910013036U (en
Inventor
오봉인
노준항
김용철
Original Assignee
삼성코닝 주식회사
한형수
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Priority to KR2019890019728U priority Critical patent/KR960001471Y1/en
Publication of KR910013036U publication Critical patent/KR910013036U/en
Application granted granted Critical
Publication of KR960001471Y1 publication Critical patent/KR960001471Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

세라믹패키지Ceramic Package

제 1 도는 종래 세라믹패키지의 평면도1 is a plan view of a conventional ceramic package

제 2 도는 제 1 도의 정면도FIG. 2 is a front view of FIG. 1

제 3 도는 제 2 도의 요부확대도3 is an enlarged view of the main part of FIG. 2

제 4 도는 본 고안의 세라믹패키지의 정면도4 is a front view of the ceramic package of the present invention

제 5 도는 제 4 도의 요부확대도이다.5 is an enlarged view illustrating main parts of FIG. 4.

본 고안은 세라믹패키지의 가장자리에 단차를 두어 칩 발생을 최소화시킬 수 있는 반도체소자 실장용 세라믹패키지에 관한 것이다.The present invention relates to a ceramic package for mounting a semiconductor device that can minimize chip generation by placing a step on the edge of the ceramic package.

일반적으로 반도체소자 실장용 세라믹패키지의 가장자리는 공정 및 금형상의 복잡화를 피하기 위해 단순한 라운딩처리만으로 마무리된다.In general, the edge of the ceramic package for semiconductor device mounting is finished with a simple rounding process to avoid complicated process and mold.

그러나 이 경우에는 세라믹패키지를 적재하거나 운반할때 가장자리에서의 칩 또는 크랙이 발생되는 문제점이 있게된다.In this case, however, there is a problem that chips or cracks are generated at the edges when the ceramic package is loaded or transported.

이러한 문제점을 고러하여 근래에 제안된 세라믹패키지의 구조가 제 2 도 및 제 3 도에 나타나있다.In view of these problems, the structure of the ceramic package proposed recently is shown in FIGS. 2 and 3.

여기에서 알 수 있는 바와 같이, 세라믹페키지의 상면 가장자리에 단차를 형성하고, 이 단차에 의해 형성되는 3위치의 모서리를 라운딩처리하고 있다.As can be seen here, a step is formed at the top edge of the ceramic package, and the corners of the three positions formed by the step are rounded.

이러한 개선된 세라믹패키지의 가장자리구조는 종래의 세라믹패키지에 비해 칩발생 및 크랙현상을 현저히 줄일 수 있게는 되었으나 그 성형공정이 까다롭고 또한 성형불량을의 증가를 가져오게 된다.The edge structure of the improved ceramic package can significantly reduce chip generation and cracking, compared to the conventional ceramic package, but the molding process is difficult and also leads to an increase in molding defects.

이에 본 고안은 칩 또는 크랙발생율을 최소화시킬 수 있으면서 성형작업 및 그 수율을 향상시킬 수 있는 반도체소자 실장용 세라믹패키지의 구조릍 제공하는데 그 안출 목적이 있다.Therefore, the present invention aims to provide a structure of a ceramic package for mounting a semiconductor device that can minimize a chip or crack occurrence rate and improve a molding operation and a yield thereof.

이하, 첨부한 도면을 참고로 하여 본 고안의 실시예를 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

제 4 도 및 제 5 도에서 나타내고 있는 바와 같이, 세라믹패키지의 가장자리에 단차를 형성하되, 패키지상면쪽으로의 단차면을 일정한 각도(θ)폭의 경사면으로 형성한다.As shown in FIG. 4 and FIG. 5, a step is formed at the edge of the ceramic package, and the step surface toward the package upper surface is formed as an inclined surface having a constant angle [theta] width.

즉, 세라믹패키지의 두께(t) 보다 얇은 두께를 갖는 모서리가 형성되도록 단차높이(A)를 0.05 ∼ 0.33mm로 한정하여 단차부를 형성시키고, 이 단차부 단차면의 경사각(θ)을 30°∼75°로 한정 성형시키며, 세라믹패키지의 폭(c)는 0.08 ∼ l.56mm로 설정된다.That is, the step height A is limited to 0.05 to 0.33 mm to form a corner having a thickness thinner than the thickness t of the ceramic package, thereby forming a stepped portion, and the inclination angle θ of the stepped step surface is 30 ° to Limited to 75 °, the width c of the ceramic package is set to 0.08 to l.56 mm.

이상의 구조로된 본 고안의 세라믹패키지와 종래의 세라믹패키지릍 시험하여 비교한 결과를 다음 표1에 나타낸다.Table 1 shows the results of comparing the ceramic package of the present invention with the above structure and the conventional ceramic package.

[ 표 1]TABLE 1

이 시험은 종래의 세라믹패키지와 본 고안의 세라믹패키지시편 각각 200개를 세라믹패키지 지지체에 별개로 10개씩 놓은 후, 이 지지체를 수직면방향, 5주기의 180℃/초의 각 속도로 회전시키며, 이때 칩결합과 균열이 발생한 시편의 수를 결정하므로서 수행했다.In this test, each of the conventional ceramic package and 200 ceramic package specimens of the present invention is placed on the ceramic package support 10 separately, and then the support is rotated at a rate of 180 ° C./sec in the vertical direction and 5 cycles. This was done by determining the number of specimens in which bonding and cracking occurred.

상기 표1로부터 본 고안의 세라믹패키지의 불량은 200개중 2개가 발생함으로써 종래의 세라믹패키지의 불량200중 34개 보다 그 불량률이 현저히 감소되었다.From the above Table 1, the defects of the ceramic package of the present invention are two out of 200, so that the defective rate is significantly reduced than that of 34 of the defects 200 of the conventional ceramic package.

상기한 구성에 따라 세라믹패키지 성형 및 춰급시에 발생되는 칩 및 크랙(crack) 현상을 최소화시킬 수 있으므로 반도체장치에 대한 신뢰성을 향상시킬 수 있는 효과를 갖는다.According to the above configuration, it is possible to minimize chip and crack phenomena generated during the molding and charging of the ceramic package, thereby improving the reliability of the semiconductor device.

Claims (1)

반도체실장용 세라믹패키지에 있어서,In the ceramic package for semiconductor mounting, 상기 세라믹패키지의 모서리에 단차부를 형성시키되,To form a stepped portion in the corner of the ceramic package, 패키지의 두께(t)보다 얇은 모서리가 형성되도록 0.05∼ 0.33mm의 단차높이(A)로 하고, 이 단차부 단차면의 경사각(θ)을 30°∼ 75°로 설정하며, 세라믹패키지의 폭(c)을 0.08 ∼ 1.56mm로 설정하는 것을 특징으로 하는 반도체실장용 세라믹패키지.The step height A of 0.05 to 0.33 mm is formed so that an edge thinner than the thickness t of the package is formed, the inclination angle θ of the step surface of the step part is set to 30 ° to 75 °, and the width of the ceramic package ( c) is set to 0.08 to 1.56mm, the ceramic package for semiconductor mounting.
KR2019890019728U 1989-12-23 1989-12-23 Seramic package KR960001471Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019890019728U KR960001471Y1 (en) 1989-12-23 1989-12-23 Seramic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019890019728U KR960001471Y1 (en) 1989-12-23 1989-12-23 Seramic package

Publications (2)

Publication Number Publication Date
KR910013036U KR910013036U (en) 1991-07-30
KR960001471Y1 true KR960001471Y1 (en) 1996-02-17

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KR2019890019728U KR960001471Y1 (en) 1989-12-23 1989-12-23 Seramic package

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KR910013036U (en) 1991-07-30

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