KR960001043Y1 - Glitch preventing decoder - Google Patents

Abstract

No content.

Description

Glitch Prevention Decoder

1 is a conventional 2x4 decoder circuit diagram.

2 is a relationship diagram of output according to input in FIG.

FIG. 3 is a waveform diagram showing respective parts of FIG. 1

4 is a glitch preventing decoder of the present invention.

FIG. 5 is a waveform diagram showing respective parts of FIG. 4

* Explanation of symbols for main parts of the drawings

I1, I2: Inbuffer ND1 to ND4: NAND gate

tpd: Transmission delay time of inverters I1 and I2 and first NAND gate ND1

The present invention relates to a glitch-prevention decoder, and more particularly, to a glitch-prevention decoder which produces a stable output by a logic combination of a gate employing a feedback when an input of a decoder is simultaneously changed.

In general, glitch refers to a phenomenon in which an output is unstable at a short time due to a delay in the transmission of circuit elements for each input when the input signals change at the same time, and acts as a direct element causing malfunction in a digital circuit.

This phenomenon also occurs in the conventional decoder circuit, and its configuration is as shown in FIG. 1 and the inverters I1, I2 for inverting the input signals A1, A0, the inverters I1, NAND combining the output signal of I2 to output the output signal y0, and NAND combining the output signal of the input signal A0 and the inverter I1 to the output signal y1. A second NAND gate ND2 to be output to the NAND, a third NAND gate ND3 to output the output signal y2 by NAND combining the output signal of the inverter I2 and the input signal A1, and The fourth NAND gate ND4 outputs the output signal y3 by NAND combining the input signals A1 and A0.

The operation and the glitch phenomenon of the conventional decoder circuit as described above will be described in detail.

In general, the NAND gate goes low when only a high level signal is applied to its input terminal. If only one low signal is included in the input signal, the output goes high.

Therefore, the output signals y0 to y3 output from the NAND gates ND1 to ND4 depending on the state of the input signals A1 and A0 become as shown in the table of FIG.

That is, when the input signals A1 and A0 are input as "0", only the output signal y0 is output at low potential, and when it is input as "1", only the output signal y1 is output at low potential and "1". When input to "", only the output signal y2 is output at low potential, and when input to "11", only output signal y3 becomes low potential.

By the way, when the input signals A1 and A0 are input at the same time as in the waveform diagram of FIG. 3 at the same time, the output signals y1 and y2 of the second and third NAND gates ND2 and ND3 are temporarily turned to low potential. An unstable operation of falling and then changing back to high potential occurs. This phenomenon occurs at the outputs of all NAND gates ND1 to ND3 except the fourth NAND gate ND4 when both input signals A1 and A0 are inverted at the same time. It becomes possible.

Therefore, there is a problem that may cause a malfunction of the entire system if the decoder circuit as described above is used as it is connected to the external circuit.

Accordingly, in order to solve the above-mentioned problems, the present invention devises a stable output from which glitches have been removed by forming a mutual feedback loop of each NAND gate constituting the output terminal of the decoder. Detailed description with reference to the following.

FIG. 4 is a glitch-prevention decoder circuit diagram of the present invention. As shown here, in the conventional circuit of FIG. 1, the output signal y0 of the first NAND gate ND1 is set as the second and third NAND gates ND2 and ND3. Input to the first and fourth NAND gates ND1 and ND4, and the output y2 of the second NAND gate ND2 to the first and fourth NAND gates ND3. The present invention is configured by inputting the NAND gates ND1 and ND4 and connecting the output y3 of the fourth NAND gate ND4 to the second and third NAND gates ND2 and ND3. The effect of the operation will be described in detail as follows.

The output signals y0 to y3 output from the NAND gates ND1 to ND4 in accordance with the input signals A1 and A0 are as described above.

That is, when the input signals A1 and A0 are "0", the output signals y3 to y0 are maintained as "1110". If the input signals A1 and A0 are inverted from "0" to "11" simultaneously, the inverter Inverted input signals applied to one input terminal G2 of the second NAND gate ND2 and one input terminal G3 of the third NAND gate ND3 due to the propagation delay characteristics of (I1, I2), respectively. Since it arrives later than the input signals A0 and A1 of the other input terminals G3 and G2, the outputs y1 and y2 of the NAND gates ND2 and ND3 may cause glitches.

However, since the first NAND gate ND1, which remained low when the input signals A1 and A0 were in the "0" state, has a propagation delay characteristic, the input signals A1 and A0 are set to "0". Even if it is changed to "11" at the same time, its output signal y0 is not instantly inverted from the low potential to the high potential and remains at the low potential for a predetermined time.

As shown in the timing diagram of FIG. 5, the input signals A1 and A0 not passing through the inverters I1 and I2 are inverted input signals passing through the inverters I1 and I2. Even if the second and third NAND gates ND2 and ND3 are reached earlier, the output signal y0 of the first NAND gate ND1 remains constant for a predetermined time (the delay time of the inverters I1 and I2 + the first NAND gate). Since the state of " 0 " is maintained as it is during the delay time of (ND1), the output signals y1 and y2 of the NAND gates ND2 and ND3 remain unchanged and thus the glitch does not appear. .

Thus, even if the input signal inverted by the transfer delay of the inverters I1 and I2 reaches a specific NAND gate later than the non-inverting input signal, a low potential signal is applied to the NAND gate during the time that the glitch occurs. The state of this high level is kept constant, which is the same for each of the NAND gates ND1 to ND4.

That is, when the input signals A1 and A0 change from "0" to "11", the glitches of the second and third NAND gates ND2 and ND3 are determined by the output signal y0 of the first NAND gate ND1. When the input signals A1 and A0 change from "1" to "10", the glitch of the first and fourth NAND gates ND1 and DN4 is determined by the output signal y1 of the second NAND gate ND2. When the input signals A1 and A0 change from "10" to "1", the first and fourth NAND gates ND1 and ND4 are output by the output signal y2 of the third NAND gate ND3. Output signals y0 and y3 are fixed at high potential, and when the input signals A1 and A0 change from "11" to "0", the second output signal y3 of the fourth NAND gate ND4 is applied. In this way, the glitching phenomenon of the third NAND gates MD2 and ND3 is eliminated, and a circuit free of glitches can be configured for the n × 2 ⁿ decoder by the above method.

As described above, the present invention provides an output of a gate having a low level value to a gate where a glitch is generated when an input signal is input with a certain time difference to a specific gate due to a propagation delay of a circuit element in an n × 2 ⁿ decoder. By keeping the input constant during the time that the glitch is generated, it is possible to raise the glitch phenomenon due to the delay of the circuit element.

Claims (1)

(Correction) Inverters I1 and I2 for inverting the input signals A1 and A0, respectively, and input signals inverted in the inverters I1 and I2, respectively. And the signal with respect to the input signals A1 and A0 , ( A0), (A1, ), (A1, A0) to NAND gates (ND1), (ND2), (ND3), and (ND4) that output the output signals (y0), (y1), (y2), and (y3) by NAND combination, respectively. In the decoder circuit configured, the output signals y0, y1, y2, and y3 are converted into the NAND gates ND2, ND3, ND1, ND4, ND1, ND4, ND2, and ND3. A glitch preventing decoder characterized in that it is connected to each of the input terminals of the common input.