KR19980076639A - Delay adjustment circuit - Google Patents

Abstract

The present invention relates to a delay adjustment circuit, comprising: a plurality of inverters that receive a predetermined signal from an external input terminal, output a predetermined delayed signal from a final output terminal, and delay each of the input signals to the next stage; A plurality of capacitor adjusting units each receiving a predetermined delayed signal from each of the plurality of inverters, and outputting a predetermined delayed signal as an input signal of a next inverter, respectively, the plurality of capacitor adjusting units, respectively, in series mode and And a plurality of mode conversion registers for outputting a predetermined bit value to each of the plurality of capacitor adjusters to be one of the parallel mode and the pass mode, thereby adjusting the delay value due to a process error to a desired delay value. Can change the delay value to account for various characteristics Can be mad.

Description

A Delay Control Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay adjustment circuit, and more particularly, to a delay adjustment circuit for obtaining various predetermined delayed output signals by changing a capacitor value by a predetermined input signal.

1 is a conventional delay circuit diagram.

Referring to FIG. 1, a conventional delay circuit includes a plurality of inverters INV1INV10 and a plurality of capacitors C1C10 respectively connected between the inverters INV1INV10.

In such a conventional delay circuit, since the value of each stage is determined and the number of stages is determined from the design, it is often the case that the parameters used in the simulation of the circuit do not coincide with the process parameters.

As a result, unwanted delay values are obtained, resulting in problems in circuit characteristics.

In addition, even if a desired characteristic is obtained without a process problem in a delay circuit, when a delay value is changed in order to take into account various other characteristics, it is difficult to perform due to a singular constraint.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and provides a delay adjustment circuit that can change an unwanted delay value caused by a single stage limitation of a delay circuit and a process problem into a desired delay value. There is this.

Another object of the present invention is to provide a delay adjustment circuit that can change the delay value in order to consider various characteristics.

1 is a conventional delay circuit diagram;

2 is a delay adjustment circuit diagram according to an embodiment of the present invention;

3 is a detailed circuit diagram illustrating a capacitor adjusting unit of FIG. 2.

* Explanation of symbols for the main parts of the drawings

INV1INV20: Inverter C1C10: Capacitor

C11: first capacitor C12: second capacitor

110: capacitor adjustment unit RG1 RG10: mode conversion register

MN1MN4: NMOS transistor MP1MP4: PMOS transistor

(Configuration)

According to a feature of the present invention proposed to achieve the above object, a delay adjustment circuit receives a predetermined signal from an external input terminal, outputs a predetermined delayed signal from a final output terminal, A plurality of inverters which are delayed and output to the next stage; A plurality of capacitor adjusting units each receiving a predetermined delayed signal from each of the plurality of inverters, and outputting a predetermined delayed signal as an input signal of a next inverter, respectively; And a plurality of mode conversion registers respectively outputting a predetermined bit value to the plurality of capacitor adjusting units such that the plurality of capacitor adjusting units are in any one of a serial mode, a parallel mode, and a pass mode.

In a preferred embodiment of the present invention, the plurality of capacitor adjusting units each include a first NMOS transistor having a gate terminal connected to a first mode conversion signal input terminal, and a current path connected between a delay signal input terminal and a delay signal output terminal. Wow; A first PMOS transistor and a second NMOS transistor having a gate terminal connected to the second mode conversion signal input terminal and each current path connected to a current path of the first NMOS transistor; A second PMOS transistor having a common gate terminal with the first PMOS transistor, and having a current path coupled between a current path of the first PMOS transistor and a second NMOS transistor; A first capacitor having one end connected to a current path of the first PMOS transistor; A second capacitor having one end connected to a current path of the second NMOS transistor; A third PMOS transistor having a current path connected to the other ends of the first and second capacitors and having a common bulk terminal with the second PMOS transistor; A third NMOS transistor connected between a current path of the second PMOS transistor and a current path of the third PMOS transistor, the third NMOS transistor having a common gate terminal with the second NMOS transistor; A fourth NMOS transistor having a current path connected between the other end of the first capacitor and a ground terminal and having a common gate terminal with the second NMOS transistor; A current path is connected between the other end of the second capacitor and the ground terminal, and includes a fourth PMOS transistor having a common gate terminal with the third PMOS transistor.

In a preferred embodiment of this aspect, the plurality of capacitor adjusting unit receives a high level signal and a low level signal, respectively, from the mode conversion register to the first and second mode conversion signal input terminals, respectively. The second capacitor is connected in parallel to output a predetermined delay signal according to the connection state of the two capacitors through the delay signal output terminal.

In a preferred embodiment of this aspect, the plurality of capacitor adjusting unit receives a high level signal from the mode conversion register to the first and second mode conversion signal input terminals, respectively, and the first and second capacitors are connected in series. In the connected state, a predetermined delay signal corresponding to the connection state of the two capacitors is output through the delay signal output terminal.

In a preferred embodiment of the present invention, the plurality of capacitor adjusting units receive a low level signal from the mode conversion register to the first mode conversion signal input terminal and receive a signal input from the delay signal input terminal. And outputs the delayed signal output terminal as it is without passing through the second capacitor.

(Action)

The present invention relates to a delay adjustment circuit, comprising: a plurality of inverters that receive a predetermined signal from an external input terminal, output a predetermined delayed signal from a final output terminal, and delay each of the input signals to the next stage; A plurality of capacitor adjusting units each receiving a predetermined delayed signal from each of the plurality of inverters, and outputting a predetermined delayed signal as an input signal of a next inverter, respectively, the plurality of capacitor adjusting units, respectively, in series mode and A plurality of mode conversion registers for outputting a predetermined bit value to each of the plurality of capacitor adjusting units to be in one of the parallel mode and the pass mode, thereby adjusting the delay value due to a process error to a desired delay value. Can change the delay value to account for various characteristics Can.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 3.

2 is a delay adjustment circuit diagram according to an embodiment of the present invention.

Referring to FIG. 2, a delay adjustment circuit according to an embodiment of the present invention includes a plurality of inverters INV11INV20, a plurality of capacitor adjusting units 110, and a plurality of mode conversion registers RG1RG10. The delay value can be changed to the desired delay value, and the delay value can be intentionally changed to consider various other characteristics.

The plurality of inverters INV11INV20 receive a predetermined signal from an external input terminal, output a predetermined delayed signal from a final output terminal, delay each of the input signals to the next stage, and output the plurality of capacitors. The adjusting unit 110 receives a predetermined delayed signal from each of the plurality of inverters INV11INV20, and outputs the predetermined delayed signal as an input signal of the next inverter, respectively.

In addition, the plurality of mode conversion registers RG1RG10 may be configured such that the capacitor adjusting unit 110 has any one of a serial mode, a parallel mode, and a pass mode. Two bit values, which are converted so as to be converted, are output to the plurality of capacitor adjusting units 110, respectively.

3 is a detailed circuit diagram illustrating the capacitor adjusting unit 110 of FIG. 2.

Referring to FIG. 3, each of the plurality of capacitor adjusting units 110 has a gate terminal connected to a first mode conversion signal input terminal en, and between a delay signal input terminal A and a delay signal output terminal Y. A first NMOS transistor MN1 having a current path connected thereto, a gate terminal connected to the second mode conversion signal input terminal X, and a respective current path connected to a current path of the first NMOS transistor MN1. The first PMOS transistor MP1 and the second NMOS transistor MN2, the first PMOS transistor MP1 and a common gate terminal, the current of the first PMOS transistor MP1 and the second NMOS transistor MN2 And a second PMOS transistor MP2 connected between current paths.

The first capacitor C11 has one end connected to the current path of the first PMOS transistor MP1, the second capacitor C12 connected to one end of the current path of the second NMOS transistor MN2, and the first capacitor C11 connected to the current path of the second PMOS transistor MP1. A current path is connected to the other ends of the first and second capacitors C11 and C12, and includes a third PMOS transistor MP3 having a common bulk terminal with the second PMOS transistor MP2.

In addition, a current path is connected between the current path of the second PMOS transistor MP2 and the current path of the third PMOS transistor MP3, and has a third NMOS having a common gate terminal with the second NMOS transistor MN2. A fourth NMOS transistor MN4 having a common gate terminal connected to a current path between the transistor MN3, the other end of the first capacitor C11, and a ground terminal, and having a common gate terminal with the second NMOS transistor MN2; A current path is connected between the other end of the second capacitor C12 and the ground terminal, and includes a fourth PMOS transistor MP4 having the common gate terminal and the third PMOS transistor MP3.

The plurality of capacitor adjusting units 110 may include a high level signal and a low level from the mode conversion register RG1RG10 to the first and second mode conversion signal input terminals en and X, respectively. The signal is input to each other, and the first and second capacitors C11 and C12 are connected in parallel, and the delay signal output terminal Y receives a predetermined delay signal according to the connection state of the two capacitors C11 and C12. Through).

The capacitor adjusting unit 110 receives a high level signal from the mode conversion register RG1RG10 to the first and second mode conversion signal input terminals en and X, respectively. The two capacitors C11 and C12 are connected in series to output a predetermined delay signal according to the connection state of the two capacitors C11 and C12 through the delay signal output terminal Y.

In addition, the plurality of capacitor adjusting units 110 receives a low level signal from the mode conversion register RG1RG10 to the first mode conversion signal input terminal en, and the second mode conversion signal input terminal X. Irrespective of the signal input to the signal, the signal input from the delay signal input terminal A is output through the delay signal output terminal Y without passing through the first and second capacitors C11 and C12.

The capacitor adjusting unit 110 as described above adjusts the delay value by adjusting the values of the capacitors C11 and C12 with the two bit values received from the plurality of mode conversion registers RG1RG10.

The following is a table showing the mode conversion state of the plurality of capacitor adjustment unit 110 according to the two-bit value of the mode conversion register (RG1RG10) input to the first and second mode conversion signal input terminal (en, X). .

TABLE 1

Referring to Table 1, when the signal input to the first mode conversion signal input terminal en is a high level signal 1, the signal is input according to the input signal of the second mode conversion signal input terminal X. The series connection or parallel connection of the first and second capacitors C11 and C12 is determined, so that the final capacitor value can be changed.

In addition, the signal input to the first mode conversion signal input terminal en may be converted into a pass mode without the first and second capacitors C11 and C12.

In the delay adjustment circuit as described above, since an output signal finally outputs through various stages of the plurality of inverters INV11INV20 and the plurality of capacitor adjusting units 110 is determined by the capacitor combination of each stage, a process problem or delay may be caused. In order to adjust the value, various delay values may be obtained according to bit values of the plurality of registers RG1RG10.

The present invention solves the problem that a conventional delay circuit has an unwanted delay value due to a singular constraint and a process error, and a problem in which the value can not be adjusted when the delay value is intentionally changed. The delay value due to the error can be adjusted to the desired delay value, and the delay value can be changed to consider various characteristics.

Claims (5)

In the delay circuit, A plurality of inverters INV11INV20 for receiving a predetermined signal from an external input terminal, outputting a predetermined delayed signal from a final output terminal, and delaying each of the input signals to the next stage; A plurality of capacitor adjusting units 110 for receiving predetermined delayed signals from each of the plurality of inverters INV11INV20 and outputting predetermined delayed signals as input signals of a next inverter, respectively; A plurality of mode conversion registers respectively outputting a predetermined bit value to the plurality of capacitor adjusting units 110 such that the plurality of capacitor adjusting units 110 are in one of a serial mode, a parallel mode, and a pass mode, respectively. RG1RG10). The method of claim 1, Each of the plurality of capacitor adjusting units 110 includes a gate terminal connected to a first mode conversion signal input terminal en and a current path connected between a delay signal input terminal A and a delay signal output terminal Y, respectively. 1 NMOS transistor MN1; A first PMOS transistor MP1 and a second NMOS transistor MN2 having a gate terminal connected to the second mode conversion signal input terminal X and each current path connected to a current path of the first NMOS transistor MN1. )Wow; A second PMOS transistor (MP2) having a common gate terminal with the first PMOS transistor (MP1) and having a current path connected between the current paths of the first PMOS transistor (MP1) and the second NMOS transistor (MN2); A first capacitor C11 having one end connected to a current path of the first PMOS transistor MP1; A second capacitor C12 having one end connected to a current path of the second NMOS transistor MN2; A third PMOS transistor (MP3) having a current path connected to the other ends of the first and second capacitors (C11, C12) and having a common bulk terminal with the second PMOS transistor (MP2); A third NMOS transistor having a common gate terminal connected to the current path between the current path of the second PMOS transistor MP2 and the current path of the third PMOS transistor MP3. MN3); A fourth NMOS transistor (MN4) having a current gate connected between the other end of the first capacitor (C11) and a ground terminal and having a common gate terminal with the second NMOS transistor (MN2); Delay adjustment, characterized in that the current path is connected between the other terminal of the second capacitor (C12) and the ground terminal, and the fourth PMOS transistor (MP4) having a common gate terminal and the third PMOS transistor (MP3) Circuit. The method of claim 2, The plurality of capacitor adjusting units 110 receives a high level signal and a low level signal from the mode conversion register RG1RG10 to the first and second mode conversion signal input terminals en and X, respectively. And the second capacitors C11 and C12 are connected in parallel to output a predetermined delay signal according to the connection state of the two capacitors C11 and C12 through the delay signal output terminal Y. Delay adjustment circuit. The method of claim 2, The plurality of capacitor adjusting units 110 receives high level signals from the mode conversion register RG1RG10 to the first and second mode conversion signal input terminals en and X, respectively, and the first and second capacitors. (C11, C12) is in series connection state, and outputs a predetermined delay signal according to the connection state of the two capacitors (C11, C12) through the delay signal output terminal (Y). The method of claim 2, The plurality of capacitor adjusting units 110 receives a low level signal from the mode conversion register RG1RG10 to the first mode conversion signal input terminal en and receives the signal input from the delay signal input terminal A. Delay adjustment circuit, characterized in that the output via the delay signal output terminal (Y) without passing through the first and second capacitors (C11, C12).