KR960000698B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
KR960000698B1
KR960000698B1 KR1019920014695A KR920014695A KR960000698B1 KR 960000698 B1 KR960000698 B1 KR 960000698B1 KR 1019920014695 A KR1019920014695 A KR 1019920014695A KR 920014695 A KR920014695 A KR 920014695A KR 960000698 B1 KR960000698 B1 KR 960000698B1
Authority
KR
South Korea
Prior art keywords
photoresist
layer
bonding pad
forming
semiconductor device
Prior art date
Application number
KR1019920014695A
Other languages
Korean (ko)
Other versions
KR940004763A (en
Inventor
전홍섭
Original Assignee
금성일렉트론주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론주식회사, 문정환 filed Critical 금성일렉트론주식회사
Priority to KR1019920014695A priority Critical patent/KR960000698B1/en
Publication of KR940004763A publication Critical patent/KR940004763A/en
Application granted granted Critical
Publication of KR960000698B1 publication Critical patent/KR960000698B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

passivating a photoresist on a protecting film by forming the protecting film on a bonding pad after forming the bonding pad on a silicon wafer; exposing the photoresist using a mask; restricting the bonding pad by developing the exposed photoresist; depositing a metal bump forming layer by a screen printed on a oxidating prevention layer formed on the bonding pad after continuously depositing adhesion layer, main bonding layer and oxidating prevention layer o the photoresist and bonding pad; forming a metal bump through a reflow furnace by eliminating the photoresist.

Description

반도체 장치 제조방법Semiconductor device manufacturing method

제1도의 (a) 내지 (f)는 종래 반도체 장치 제조 공정도.(A)-(f) of FIG. 1 is a manufacturing process diagram of a conventional semiconductor device.

제2도의 (a) 내지 (g)는 종래 반도체 장치 제조에 대한 다른 실시 공정도.(A)-(g) of FIG. 2 is another implementation process diagram for manufacturing a conventional semiconductor device.

제3도의 (a) 내지 (g)는 본 발명 반도체 장치 제조 공정도.(A)-(g) of FIG. 3 is a manufacturing process diagram of this invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 웨이퍼 2 : 본딩패드1 silicon wafer 2 bonding pad

3 : 보호막 4 : 포토레지스터3: protective film 4: photoresist

5 : 마스크 6 : 접착층5: mask 6: adhesive layer

7 : 메인본딩층 8 : 산화방지층7 main bonding layer 8 antioxidant layer

9 : 금속범프형성층 10 : 금속범프9: metal bump forming layer 10: metal bump

11 : 스크린프린트 마스크 12 : 스퀴저11: screenprint mask 12: squeezer

13 : 땜납13: solder

본 발명은 금속범프(Metal Bump)에 관한 것으로, 특히 금속범프를 스크린 프린트 방법으로 제조함으로써 제조공정을 쉽고 간단하게 하고, 생산성을 향상시키는데, 적당하도록한 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal bumps, and more particularly, to a method of manufacturing a semiconductor device that is suitable for making the manufacturing process easy and simple, and improving productivity by manufacturing the metal bumps by a screen printing method.

일반적으로 웨이퍼위에 금속범프를 형성시키는 기술은 두가지로 구분할 수 있다.In general, there are two techniques for forming metal bumps on a wafer.

첫째는 기초 구성물질(Base Material)을 증착(Evaporation)시킨 후 포토레지스터(Photo Resistor : PR)를 제거(Lift-off)시키는 방법이고, 둘째는 전기도금 (Electroplating)시키는 방법이다.The first method is to remove the photoresist (PR) after evaporation of the base material, and the second is to electroplating.

상기의 방법으로 금속범프를 제조하는 공정을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, the process of manufacturing a metal bump in the above method in detail as follows.

먼저 기초 구성물질 증착(Evaporation)후 포토레지스터(PR)를 제거하는 방법을 설명한다.First, a method of removing the photoresist (PR) after evaporation of the basic component is described.

제1도의 (a) 내지 (f)는 종래 반도체 장치 제조 공정도로서, 제1도의 (a)에 도시된 바와같이 깨끗하게 세척하여 건조시킨 실리콘 웨이퍼(1)위에 금속(Al)을 증착한 후 패터닝하여 본딩패드(Bonding Pad)(2)을 형성시키고, 그 본딩패드(2)위에 보호막(3)을 증착한 후 패턴을 형성하고, 상기 보호막(3)위에 포토레지스터(4)를 도포한다.(A) to (f) of FIG. 1 are conventional process diagrams for manufacturing a semiconductor device. As shown in (a) of FIG. 1, metal (Al) is deposited and patterned on a clean and dried silicon wafer (1). A bonding pad 2 is formed, a protective film 3 is deposited on the bonding pad 2, a pattern is formed, and a photoresist 4 is coated on the protective film 3.

그후 제1도의 (b)에 도시된 바와같이 도포된 상기 포토레지스터(4)를 마스크(5)를 사용해서 노출(Exposure)시킨 후 제1도의 (c)에 도시된 바와같이 상기 포토레지스터(4)를 현상(Develop)하여 상기 본딩패드(2)를 한정하고, 그후 제1도의 (d)에 도시된 바와같이 상기 포토레지스터(4)와 상기 본딩패드(2)위에 기초구성물질을 이루는 접착층(6), 메인본딩층(7), 산화방지층(8)을 연속 증착한 다음 제1도의 (e)에 도시된 바와같이 상기 산화방지층(8)위에 금속범프로 사용되는 금속범프형성층(9)을 두껍게 증착한 후 상기 포토레지스터(4)를 제거하고, 그후 제1도의 (f)에 도시된 바와 같이 상기 실리콘웨이퍼(1)를 리플로우 퍼니스(Reflow furnace)를 통과시켜 구형의 금속범프(10)를 형성함으로써 반도체 장치를 제조한다Thereafter, the photoresist 4 applied as shown in FIG. 1B is exposed using a mask 5, and then the photoresist 4 as shown in FIG. 1C. (Develop) to define the bonding pad (2), and then, as shown in (d) of FIG. 1, an adhesive layer forming a basic material on the photoresist (4) and the bonding pad (2) ( 6), the main bonding layer 7 and the anti-oxidation layer 8 are successively deposited, and then the metal bump forming layer 9, which is used as a metal bump on the anti-oxidation layer 8, as shown in FIG. After deposition, the photoresist 4 is removed, and the silicon wafer 1 is passed through a reflow furnace as shown in FIG. A semiconductor device is manufactured by forming

두번째로, 전기도금(Electroplating)방법을 설명하면 다음과 같다.Second, the electroplating method is described as follows.

제2도의 (a) 내지 (g)는 종래 반도체 장치 제조 공정도로서, 제2도의 (a)에 도시된 바와 같이 깨끗하게 세척하여 건조시킨 실리콘웨이퍼(1)위에 금소(Al)을 증착한 후 패터닝하여 본싱패드(2)를 형성하고, 그 위에 보호막(3)을 증착한 후 패턴을 형성하며, 상기 보호막(3)위에 기초구성물질로 이루어진 접착층(6), 메인본딩층(7), 산화방지층(8)을 연속해서 증착하고 그후 제2도의 (b)에 도시된 바와같이 상기 산화방지층 (8)위에 포토레지스터(4)를 도포한 다음 마스크(5)를 사용해서 상기 포토레지스터(4)를 노출(Exposure)시키고, 제2도의 (c)에 도시된 바와같이 상기 노출된 포토레지스터 (4)를 현상(Develop)하여 상기 본댕패드(2)를 한정한다 그후 제2도의 (d)에 도시된 바와같이 상기 포토레지스터(4)를 마스크로 사용해서 전기도금(Electroplating)하여 상기 산화방지층(8)위에 금속범프 형성층(9)을 형성시킨 다음 제2도의 (e)에 도시된 바와 같이 상기 포토레지스터(4)를 제거하고,그후 제2도의 (f)에 도시된 바와 같이 상기 접착층(6), 메인본딩층(7) 및 산화방지층(8)을 에칭한 후 제2도의 (g)에 도시된 바와같이 상기 실리콘웨이퍼(1)를 리플로우 퍼니스(Reflow frunace)를 통과시켜 구형의 금속범프(10)를 형성함으로써 반도체 장치를 제조한다.(A) to (g) of FIG. 2 are conventional process diagrams for manufacturing a semiconductor device. As shown in FIG. 2, (a), gold (Al) is deposited and patterned on a silicon wafer (1) which has been cleaned and dried. The bonding pad 2 is formed, a protective film 3 is deposited thereon, and a pattern is formed thereon. The adhesive layer 6, the main bonding layer 7, and the anti-oxidation layer of the base material are formed on the protective film 3. 8) was deposited successively, and then a photoresist 4 was applied on the antioxidant layer 8 as shown in FIG. 2 (b), and then the photoresist 4 was exposed using a mask 5. Expose and develop the exposed photoresist 4 as shown in (c) of FIG. 2 to define the bond pad (2). Then, as shown in (d) of FIG. Similarly, electroplating is performed using the photoresist 4 as a mask, on the antioxidant layer 8. After forming the metal bump forming layer 9, the photoresist 4 is removed as shown in (e) of FIG. 2, and then the adhesive layer 6, the main as shown in FIG. After etching the bonding layer 7 and the anti-oxidation layer 8, the silicon wafer 1 is passed through a reflow furnace (reflow frunace) as shown in FIG. The semiconductor device is manufactured by forming the semiconductor device.

상기에서 설명한 바와같이 상기 본댕패드(2)위에 형성된 금속범프(10)를 사용하여 실장용 기판(PCB, 세라믹, 유리등등)에 직접부착시켜 전기적으로 상호 연결시키고 있다As described above, the metal bumps 10 formed on the bond pad 2 are directly attached to a mounting substrate (PCB, ceramic, glass, etc.) and electrically connected to each other.

그러나 상기에 설명된 기초 구성물질. 즉 접착층(6), 메인본딩 층(7) 및 산화방지층(8)을 증착한 후 포토레지스터(4)를 제거하는 방법은 기초 구성물질을 증착하고 나서 그 위에 금속범프형성층(9)을 두겁게 증착시키기 위해서 장시간이 소요되기 때문에 생산성이 저하되는 문제점이 있고, 전기도금하는 방법은 금속범프형성층(9)을 증착하는데에는 단시간내에 수행할 수 있지만 도금하기 위한 화학적 전처리 공정을 수행해야 하므로 공정상 번거로움이 발생되는 문제점이 있었다.But the basic constituents described above. That is, the method of removing the photoresist 4 after depositing the adhesive layer 6, the main bonding layer 7, and the anti-oxidation layer 8 is performed by depositing the base constituent material and then thickening the metal bump forming layer 9 thereon. It takes a long time to deposit, there is a problem that productivity is lowered, and the electroplating method can be performed in a short time to deposit the metal bump forming layer (9), but the process is cumbersome because the chemical pretreatment process for plating must be performed There was a problem that remorse occurred.

본 발명은 이러한 종래의 문제점을 해결하기 위하여, 스크린 프린트 방법으로 금속범프형성층을 증착시킴으로써 단시간내에 공정이 수행되어 생산성을 증대시킬 수 있을뿐만 아니라 공정이 간단하게 이루어질 수 있도록 한 반도체 장치 제조방범을 창안한 것으로, 이를 첨부한 제3도를 참조하여 설명하면 다음과 같다.In order to solve the above problems, the present invention devises a semiconductor device manufacturing crime prevention process, which not only can increase the productivity by performing the process within a short time by depositing the metal bump forming layer by the screen printing method, but can also simplify the process. One, it will be described with reference to Figure 3 attached as follows.

제3도의 (a) 내지 (g)는 본 발명 반도체 장치 제조공정도로서 (a)에 도시한 바와같이 깨끗하게 세척하여 건조시킨 실리콘웨이퍼(1)위에 금속(Al)을 증착한 후 패터닝하여 본댕패드(2)를 형성하고, 이후 상기 본딩패드(2)위에 보호막(3)을 증착한 후 패턴을 형성하며, 이후 그 보호막(3)위에 포토레지스터(4)를 도포 한다. 이때 도포되는 상기 포토레지스터(4)는 고체(solid)나 건조(Dry)된 포토레지스터를 사용한다.(A) to (g) of FIG. 3 are process charts for manufacturing a semiconductor device of the present invention, as shown in (a), a metal (Al) is deposited on a silicon wafer (1) that has been cleaned and dried, and then patterned to form a bond pad (2). ), And then, a protective film 3 is deposited on the bonding pad 2, and then a pattern is formed. Then, a photoresist 4 is coated on the protective film 3. In this case, the photoresist 4 to be applied uses a solid or dried photoresist.

이후 제3도의 (b)에 도시한 바와 같이 상기 포토레지스터(4)를 마스크(5)를 이용하여 노출(Exposure)을 시킨 후 제3도의 (c)에 도시한 바와 같이 상기 포토레지스터 (4)를 현상(Develop)하여 상기 본딩패드(2)를 한정한다. 이후 제3도의 (d)에 도시한 바와같이 상기 포토레지스터(4)와 본딩패드(2)위에 기초 구성물질인 접착층(6), 메인 본딩층(7) 및 산화방지층(8)을 연속으로 증착시킨다.Thereafter, as shown in (b) of FIG. 3, the photoresist 4 is exposed using a mask 5, and then the photoresist 4 is illustrated as shown in (c) of FIG. 3. Is developed to define the bonding pad 2. Subsequently, as shown in FIG. 3 (d), the adhesive layer 6, the main bonding layer 7, and the antioxidant layer 8, which are the basic constituents, are sequentially deposited on the photoresist 4 and the bonding pad 2. FIG. Let's do it.

여기서 상기 접착층(6)은 크롬(Cr), 티탄(Ti), 티탄(Ti)과 턴스텐(W)의 합금이 사용되고, 상기 메인본딩층(7)은 구리(Cu), 니켈(Ni), 팔라듐(Pd)등이 사용된다. 한편, 상기 산화방지층(8)은 필요에 따라 증착시키지 않아도 된다.Here, the adhesive layer 6 may be formed of an alloy of chromium (Cr), titanium (Ti), titanium (Ti) and turnsten (W), and the main bonding layer 7 may include copper (Cu), nickel (Ni), Palladium (Pd) or the like is used. In addition, the said antioxidant layer 8 does not need to be deposited as needed.

이후 제3도의 (e)에 도시한 바와같이 상기 산화방지층(8)위에 금속범프형성층 (9)을 증착한다. 이때 상기 금속범프형성층(9)은 상기 실리콘웨이퍼(1)위의 본딩패드 (2)와 동일한 크기포 패턴이 형성된 스크린프린트 마스크(11)를 상기 산화방지층(8)위에 올려놓고, 스퀴저(12)를 좌우로 이동시키면서 상기 스크린프린트 마스크(11)위에 있는 땜납(13)을 한정된 상기 본댕패드(2)에 형성된 상기 산화방지 층(8)위에 증착하여 형성 한다.Thereafter, as shown in FIG. 3E, a metal bump forming layer 9 is deposited on the antioxidant layer 8. In this case, the metal bump forming layer 9 places the screen print mask 11 having the same size cloth pattern as the bonding pad 2 on the silicon wafer 1 on the anti-oxidation layer 8, and the squeezer 12. ) Is formed by depositing the solder 13 on the screen print mask 11 on the anti-oxidation layer (8) formed on the limited bond pad (2) while moving from side to side.

이후 제3도의 (f)에 도시한 바와같이 상기 포토레지스터(4)를 제거하고. 상기 실리콘웨이퍼(1)를 리플로우 퍼니스(Reflow furnace)로 통과시켜 구형의 금속범프 (10)를 형성시킴으로써 반도체 장치를 제조한다.Thereafter, the photoresist 4 is removed as shown in FIG. The semiconductor device is manufactured by passing the silicon wafer 1 through a reflow furnace to form a spherical metal bump 10.

이상에서 설명한 바와같이 본 발명은 기초 구성물질위에 금속 범프형성층을 스크린프린트 방법으로 증착시키기 때문에 웨이퍼를 로딩(Loading)한 후 스퀴저 (squeezer)가 좌우로 왕복하는 시간만이 소요되므로 생산성을 향상시킬 수 있고, 증착공정도 간단하게 수행할 수 있는 효과가 있다.As described above, since the present invention deposits a metal bump forming layer on the basic material by screen printing, the productivity is improved since only a time for squeezer reciprocating after loading the wafer is required. And, there is an effect that the deposition process can be performed simply.

Claims (6)

실리콘웨이퍼(1)위에 본딩패드(2)를 형성한 후 그 본딩패드(2) 위에 보호막 (3)을 형성하고. 그 보호막(3)위에 포토레지스터(4)를 도포하는 공정과, 상기 포토레지스터(4)를 마스크(59)로 사용해서 노출(Exporsure)하는 공정과, 노출된 상기 포토레지스터(4)를 현상(Develop)하여 상기 본딩패드(2)를 한정하는 공정과, 상기 포토레지스터(4)와 본딩패드(2)위에 연속으로 접착층(6), 메인본딩층(7) 및 산화방지층(8)을 증착한 후 상기 본딩패드(2)위에 형성된 상기 산화방지층(8)위에 스크린프린트방법으로 금속범프형성층(9)을 증착하는 공정과, 상리 포토레지스터(4)를 제거한 후 상기 실리콘웨이퍼(1)를 리플로우 퍼니스(Reflow furnace)를 통해 금속범프(10)를 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체 장치 제조방법.Forming a bonding pad 2 on the silicon wafer 1, and then forming a protective film 3 on the bonding pad 2; Applying a photoresist 4 on the protective film 3; exposing using the photoresist 4 as a mask 59; developing the exposed photoresist 4; And a bonding layer 6, a main bonding layer 7, and an antioxidant layer 8 are successively deposited on the photoresist 4 and the bonding pad 2, respectively. And depositing the metal bump forming layer 9 on the anti-oxidation layer 8 formed on the bonding pad 2 by a screen printing method, removing the positive photoresist 4, and then reflowing the silicon wafer 1. A method of manufacturing a semiconductor device, comprising the step of forming a metal bump (10) through a furnace (Reflow furnace). 제1항에 있어서 포토레지스터(4)는 고체(solid)로된 포토레지스터나 건조(Dry )된 포토레지스터를 사용함을 특징으로 하는 반도체 장치 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the photoresist (4) uses a solid photoresist or a dry photoresist. 제1항에 있어서, 접착층(6)은 크롬(Cr), 티탄(Ti), 티탄(Ti)과 텅스텐(W)의 합금중 하나를 사용함을 특징으로 하는 반도체 장치 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the adhesive layer (6) uses one of an alloy of chromium (Cr), titanium (Ti), titanium (Ti) and tungsten (W). 제1항에 있어서, 메인본딩층(7)은 구리 (Cu), 니켈(Ni), 팔라듐(Pd)중 하나를 사용함을 특징으로 하는 반도체 장치 제조방법.A method according to claim 1, wherein the main bonding layer (7) uses one of copper (Cu), nickel (Ni) and palladium (Pd). 제1항에 있어서, 산화방지층(8)은 필요에 따라 증착하지 않음을 특징으로 하는 반도체 장치 제조방법.A method according to claim 1, wherein the antioxidant layer (8) is not deposited as necessary. 제1항에 있어서, 금속범프형성층(9)은 땜납(13)을 사용함을 특징으로 하는 반도체 장치 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the metal bump forming layer (9) uses solder (13).
KR1019920014695A 1992-08-14 1992-08-14 Manufacturing method of semiconductor device KR960000698B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920014695A KR960000698B1 (en) 1992-08-14 1992-08-14 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920014695A KR960000698B1 (en) 1992-08-14 1992-08-14 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940004763A KR940004763A (en) 1994-03-15
KR960000698B1 true KR960000698B1 (en) 1996-01-11

Family

ID=19338019

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920014695A KR960000698B1 (en) 1992-08-14 1992-08-14 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960000698B1 (en)

Also Published As

Publication number Publication date
KR940004763A (en) 1994-03-15

Similar Documents

Publication Publication Date Title
US6992001B1 (en) Screen print under-bump metalization (UBM) to produce low cost flip chip substrate
KR100712772B1 (en) Flip chip bump bonding
JP3549208B2 (en) Integrated redistribution routing conductors, solder vipes and methods of forming structures formed thereby
JP3469686B2 (en) Method of depositing solder on printed circuit board and printed circuit board
JP4709463B2 (en) Named element
JP3618997B2 (en) How to create a metal standoff on an electronic circuit
US4640739A (en) Process of producing galvanic layers of solder of precise contour on inorganic substrates
KR20050068032A (en) Method for forming bump pad of flip-chip and the structure thereof
WO2013184028A1 (en) Method for producing conductive tracks
KR900000438B1 (en) Method of selectively depositing metal layers on a substrate
KR960000698B1 (en) Manufacturing method of semiconductor device
JPH06140409A (en) Manufacture of semiconductor device
US6576541B2 (en) Method and structure for producing bumps on an IC package substrate
JP3370663B2 (en) Semiconductor radiation detecting element array and method of forming solder bump
KR100740436B1 (en) Method for forming electrode of ceramic device using electrolytic plating
JPH0226780B2 (en)
KR960011857B1 (en) Semiconductor device and the manufacturing method
KR0154350B1 (en) Solder ball grid pad for ball grid array package and its fabrication method
JPH0799216A (en) Production of bumped circuit board
JP2006313929A (en) Method for manufacturing flip-chip ic and method for manufacturing flip-chip ic mounting circuit board
KR100274049B1 (en) Method for forming bump of wafer
JPH02303087A (en) Mounting of electronic passive element
KR950009887B1 (en) Manufacturing method of bump of semiconductor device
JPS61225839A (en) Forming method for bump electrode
JPS63164343A (en) Flip chip ic device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20041220

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee