JPH06140409A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06140409A
JPH06140409A JP4291679A JP29167992A JPH06140409A JP H06140409 A JPH06140409 A JP H06140409A JP 4291679 A JP4291679 A JP 4291679A JP 29167992 A JP29167992 A JP 29167992A JP H06140409 A JPH06140409 A JP H06140409A
Authority
JP
Japan
Prior art keywords
barrier metal
bonding pad
bump
metal
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4291679A
Other languages
Japanese (ja)
Other versions
JP2784122B2 (en
Inventor
Masahiko Tsumori
昌彦 津守
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP4291679A priority Critical patent/JP2784122B2/en
Publication of JPH06140409A publication Critical patent/JPH06140409A/en
Application granted granted Critical
Publication of JP2784122B2 publication Critical patent/JP2784122B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable forming barrier metal with a few processes, and simply form a bump, by arranging barrier metal on a bonding pad by an electroless plating method, and forming a bump on the barrier metal. CONSTITUTION:A semiconductor circuit, bonding pads 3, a passivation film 4, etc., which film is composed of, e.g. a silicon nitride film of about 1mum in thickness are formed in the state of a semiconductor wafer. The bonding pad 3 is made of metal whose main component is aluminum (some silicon or copper can be contained), and is formed to be 1mum or thicker. Barrier metal 5 is deposited on the bonding pads 3 by an electroless plating method. A bump 9 is formed on the barrier metal 5. That is, solder paste is spread and fused, thereby forming a bump of about 50-70mum in thickness. Hence remarkable reduction of manufacturing cost can be achieved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製法に関す
る。さらに詳しくは、半導体チップのボンディングパッ
ド上に簡単にバンプを形成できる半導体装置の製法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, it relates to a method of manufacturing a semiconductor device in which bumps can be easily formed on a bonding pad of a semiconductor chip.

【0002】[0002]

【従来の技術】最近、電子機器の小型化に伴ない、集積
回路(IC)などを組み込んだ半導体装置も、樹脂でモ
ールドしてリード線を導出したものではなく、半導体チ
ップのボンディングパッドにバンプが形成された半導体
装置(いわゆるベアチップ)の状態で、直接プリント基
板などの配線リードに接続して使用するものが増えつつ
ある。このような半導体装置は、図2に半導体装置のバ
ンプ部の断面図が示されるように、半導体基板21に形成
された半導体回路の外部接続用電極端子はアルミニウム
配線などで半導体チップの周縁部に導出されてボンディ
ングパッド23が形成され、前記ボンディングパッド23以
外の半導体基板21の表面には保護膜としてパッシベーシ
ョン膜24が形成され、前記ボンディングパッド23上にバ
リアメタル26を介して金属バンプ25が電解メッキ法など
により形成されている。そののち、バンプ25以外のとこ
ろのバリアメタルがエッチングされる。バリアメタル26
はたとえば、ボンディングパッドを構成する材料との密
着性がよく、バンプ金属がボンディングパッド23に、ま
たその反対にボンディングパッド金属がバンプ25に熱拡
散するのを防止する役目をもち、かつ表面が変質しにく
くバンプ金属とのなじみがよい金属が選ばれ、通常複数
層で形成されている。
2. Description of the Related Art With the recent miniaturization of electronic devices, semiconductor devices incorporating integrated circuits (ICs) are not molded with resin to lead wires, but bumps are applied to bonding pads of semiconductor chips. There is an increasing number of semiconductor devices (so-called bare chips) in which the above are formed, which are directly connected to wiring leads such as a printed circuit board for use. In such a semiconductor device, as shown in the sectional view of the bump portion of the semiconductor device in FIG. 2, the external connection electrode terminals of the semiconductor circuit formed on the semiconductor substrate 21 are formed on the peripheral portion of the semiconductor chip by aluminum wiring or the like. A lead-out bonding pad 23 is formed, a passivation film 24 is formed as a protective film on the surface of the semiconductor substrate 21 other than the bonding pad 23, and a metal bump 25 is electrolyzed on the bonding pad 23 via a barrier metal 26. It is formed by a plating method or the like. After that, the barrier metal other than the bump 25 is etched. Barrier metal 26
Has good adhesion to the material of which the bonding pad is made, has the role of preventing the bump metal from thermally diffusing to the bonding pad 23 and vice versa, and has its surface modified. A metal that is difficult to handle and has good compatibility with the bump metal is selected, and is usually formed of a plurality of layers.

【0003】このボンディングパッド23上にバンプ25を
形成する方法として、図2に示されるように、全面に
蒸着法またはスパッタ法によりバリアメタル26を形成し
たのち、バンプを形成しない部分にレジスト膜27を設
け、電解メッキ法によりバンプ25を形成したり、バリ
アメタルをフォトリソグラフィ工程でパターンニングし
てボンディングパッド上にのみ残し、メタルマスクでマ
スキングしたのち、表面全体に蒸着法またはスパッタ法
によりバンプ25を積層し、メタルマスクとともに不要な
金属材料を除去したり、また前述のパターンニングさ
れたバリアメタル26上にスクリーン印刷法などにより、
バンプ用のペースト状の金属を付着してバンプ25を形成
したりする方法がとられている。
As a method of forming the bump 25 on the bonding pad 23, as shown in FIG. 2, a barrier metal 26 is formed on the entire surface by a vapor deposition method or a sputtering method, and then a resist film 27 is formed on a portion where no bump is formed. Bumps are formed by electrolytic plating, or barrier metal is patterned by a photolithography process to leave only on the bonding pads and masked with a metal mask, and then bumps 25 are deposited on the entire surface by vapor deposition or sputtering. By removing unnecessary metal material with a metal mask, or by screen printing on the patterned barrier metal 26 described above.
A method of forming a bump 25 by attaching a paste-like metal for bumps is adopted.

【0004】[0004]

【発明が解決しようとする課題】従来のバンプの形成法
としては、主として前述ののメッキ法が用いられてい
るが、メッキ法ではバンプ金属をハンダで形成するばあ
いにハンダを溶かさずにバリアメタルのみエッチングす
ることが困難であるため、前述の、の方法が検討さ
れている。しかし、これらの方法では、前述のようにバ
リアメタルをフォトリソグラフィ工程によりバンプ形成
場所にのみ残存するように、パターニングをしなければ
ならない。そのため、バリアメタルの蒸着、レジスト塗
布、露光、レジスト現像、レジストベーキング、バリア
メタルエッチング、レジスト除去という工程を経なけれ
ばならない。そのため、製造に時間がかり、コストが高
くなる。
The above-mentioned plating method is mainly used as a conventional bump forming method. However, in the plating method, when the bump metal is formed by solder, the barrier is not melted without melting the solder. Since it is difficult to etch only metal, the above method is being studied. However, in these methods, as described above, the barrier metal must be patterned by the photolithography process so that it remains only at the bump formation location. Therefore, the steps of vapor deposition of barrier metal, resist coating, exposure, resist development, resist baking, barrier metal etching, and resist removal must be performed. Therefore, it takes time to manufacture and the cost becomes high.

【0005】さらに、バリアメタル26に使用される金な
どの材料が半導体基板21内部に侵入すると半導体基板の
シリコンにとって不純物となるため、従来の工程の装置
で蒸着するのが難かしく、別途蒸着装置などの設備が必
要になるという問題がある。
Further, if a material such as gold used for the barrier metal 26 enters the inside of the semiconductor substrate 21 and becomes an impurity for the silicon of the semiconductor substrate, it is difficult to deposit by a conventional process apparatus, and a separate vapor deposition apparatus is used. There is a problem that such equipment is required.

【0006】本発明では、かかる問題を解消し、少ない
工程でバリアメタルを形成でき、簡単にバンプを形成で
きる半導体装置の製法を提供すること目的とする。
It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves such a problem, can form a barrier metal in a small number of steps, and can easily form bumps.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置の製
法は、半導体基板に半導体回路が形成され、該半導体回
路から外部導出用の電極膜が半導体チップの周縁部に導
出されてボンディングパッドが形成され、該ボンディン
グパッド上に外部リードとの接続用のバンプが設けられ
てなる半導体装置の製法であって、前記ボンディングパ
ッド上に無電解メッキ法によりバリアメタルを設け、該
バリアメタル上にバンプを形成することを特徴とするも
のである。
According to a method of manufacturing a semiconductor device of the present invention, a semiconductor circuit is formed on a semiconductor substrate, an electrode film for external lead-out is led out from the semiconductor circuit to a peripheral portion of a semiconductor chip, and a bonding pad is formed. A method of manufacturing a semiconductor device, wherein a bump for connection to an external lead is provided on the bonding pad, a barrier metal is provided on the bonding pad by an electroless plating method, and a bump is provided on the barrier metal. Is formed.

【0008】また、前記製法においては、前記ボンディ
ングパッドを1μm以上の厚さのアルミニウムを主成分
とする金属膜から形成し、前記バリアメタルを設ける前
に前記ボンディングパッド表面をエッチングしてアルミ
ニウムを活性化することが好ましい。
Further, in the above-mentioned manufacturing method, the bonding pad is formed of a metal film having a thickness of 1 μm or more and containing aluminum as a main component, and the surface of the bonding pad is etched to activate the aluminum before the barrier metal is provided. Is preferable.

【0009】[0009]

【作用】本発明によれば、バリアメタルを無電解メッキ
法によって形成しているため、ボンディングパッド表面
のみに選択的に付着させることができ、エッチングのた
めのフォトレジスト工程を必要としない。しかも、ボン
ディングパッド上のみに付着するため、材料のムダもな
く、また無電解メッキ液に浸漬するだけで済むため、一
度に大量のバッチ処理ができる。さらにそののちのバン
プ形成もスクリーン印刷法などにより形成することによ
り、短時間でバンプを形成できる。
According to the present invention, since the barrier metal is formed by the electroless plating method, it can be selectively attached only to the surface of the bonding pad, and the photoresist process for etching is not required. Moreover, since it adheres only to the bonding pad, there is no waste of material, and since it only needs to be dipped in the electroless plating solution, a large amount of batch processing can be performed at one time. Further, the subsequent bumps can be formed in a short time by forming the bumps by a screen printing method or the like.

【0010】[0010]

【実施例】つぎに図面を参照しながら本発明について説
明する。図1は本発明の半導体装置の製法の一実施例を
説明するためのバンプ部分の断面図である。
The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a bump portion for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention.

【0011】半導体基板1に半導体回路2が形成されて
おり、該半導体回路の外部リードとの接続用の電極端子
がアルミニウムなどの金属薄膜により半導体チップの周
縁部に導出され、ボンディングパッド3が形成されてい
る。前記ボンディングパッド3以外の半導体基板1表面
には保護膜としてパッシベーション膜4が形成されてい
る。前記ボンディングパッド3上には、バリアメタル5
が形成され、その上にバンプ9が形成されている。バリ
アメタル5の形成においては、まず第1層6として、ボ
ンディングパッドの材料であるアルミニウムなどと相互
に拡散する量が小さく、密着性のよい材料、たとえば、
亜鉛、チタン、クロム、パラジウムなどの金属が付着さ
れる。また、バリアメタルの最外層8としては、表面の
酸化などの変質防止の点から金、白金などが好ましい。
このばあい、たとえばバンプ金属が第1層6またはボン
ディングパッド3に拡散するのを防止するため、バンプ
9や第1層6と相互に拡散する量が小さい、ニッケルま
たは銅などの金属からなる第2層7を第1層6と最外層
8とのあいだに介在させた三層構造で形成することが好
ましい。しかし、一層でこれらの機能を果す材料を使用
できれば一層でもよい。
A semiconductor circuit 2 is formed on a semiconductor substrate 1, and electrode terminals for connection with external leads of the semiconductor circuit are led out to the peripheral portion of a semiconductor chip by a metal thin film such as aluminum, and a bonding pad 3 is formed. Has been done. A passivation film 4 is formed as a protective film on the surface of the semiconductor substrate 1 other than the bonding pads 3. A barrier metal 5 is formed on the bonding pad 3.
Are formed, and the bumps 9 are formed thereon. In forming the barrier metal 5, first, as the first layer 6, a material having a small amount of mutual diffusion with aluminum, which is a material of the bonding pad, and good adhesion, for example,
Metals such as zinc, titanium, chromium and palladium are deposited. Further, as the outermost layer 8 of the barrier metal, gold, platinum or the like is preferable from the viewpoint of preventing alteration such as oxidation of the surface.
In this case, for example, in order to prevent the bump metal from diffusing into the first layer 6 or the bonding pad 3, a small amount of mutual diffusion with the bump 9 or the first layer 6 made of a metal such as nickel or copper is used. It is preferable to form the two layers 7 with a three-layer structure in which the two layers 7 are interposed between the first layer 6 and the outermost layer 8. However, one layer may be used as long as a material that fulfills these functions can be used.

【0012】この半導体装置を製造するには、まず半導
体回路、ボンディングパッド3およびたとえば約1μm
のチッ化シリコン膜からなるパッシベーション膜4など
を半導体ウエハの状態で通常の半導体装置の製造プロセ
スにより形成する。ここでは、ボンディングパッド3上
にバリアメタル5とバンプ9を形成する方法について説
明する。なお後述する理由によりボンディングパッド3
はアルミニウムを主成分とする金属(若干のシリコンや
銅を含んでいてもよい)を使用し、厚さが1μm以上に
形成されることが好ましい。
In order to manufacture this semiconductor device, first, the semiconductor circuit, the bonding pad 3 and, for example, about 1 μm are formed.
The passivation film 4 made of a silicon nitride film is formed in the state of a semiconductor wafer by a normal semiconductor device manufacturing process. Here, a method of forming the barrier metal 5 and the bump 9 on the bonding pad 3 will be described. The bonding pad 3 is used for the reason described below.
Is preferably made of a metal containing aluminum as a main component (may contain a small amount of silicon or copper) and has a thickness of 1 μm or more.

【0013】まず、ボンディングパッド上に無電解メッ
キ法によりバリアメタル5を堆積する。具体例として
は、Al−Siで100 μm×100 μmの大きさに1μm
以上の厚さでボンディングパッドが形成された半導体チ
ップを、水酸化ナトリウムを5重量%含むアルカリ性の
脱脂剤に25℃で約5分間浸漬して、脱脂を行った。つい
で25℃で10重量%のリン酸に約5分間浸漬し、ボンディ
ングパッドの表面をエッチング処理し、活性化させた。
この際、ボンディングパッドのアルミニウム表面が 0.5
μm程度エッチングされた。このエッチングによる損失
を考慮してボンディングパッドの厚さは前述のように1
μm以上の厚さで形成しておくことが好ましい。つぎに
25℃でジンケート処理することによりボンディングパッ
ド表面に亜鉛膜を 0.1μm程度形成した。さらに、80〜
90℃のNi−P系メッキ液で無電解ニッケルメッキを行
い、第2層7としてニッケル層を1〜1.2 μm程度形成
し、引き続き80〜90℃で無電解メッキにより0.05μm程
度の金膜を最外層として形成した。そののち、室温で約
10分間純水洗浄を行ってバリアメタル5の形成を行っ
た。
First, the barrier metal 5 is deposited on the bonding pad by electroless plating. As a specific example, Al-Si has a size of 100 μm × 100 μm and a size of 1 μm.
The semiconductor chip on which the bonding pad was formed with the above thickness was immersed in an alkaline degreasing agent containing 5% by weight of sodium hydroxide at 25 ° C. for about 5 minutes to degrease it. Then, the surface of the bonding pad was etched and activated by immersing in 10% by weight phosphoric acid at 25 ° C. for about 5 minutes.
At this time, the aluminum surface of the bonding pad is 0.5
It was etched by about μm. Considering the loss due to this etching, the thickness of the bonding pad is 1 as described above.
It is preferably formed with a thickness of μm or more. Next
A zinc film of about 0.1 μm was formed on the surface of the bonding pad by treating with zincate at 25 ° C. In addition, 80 ~
Electroless nickel plating is performed with a Ni-P based plating solution at 90 ° C to form a nickel layer of about 1 to 1.2 µm as the second layer 7, and then a gold film of about 0.05 µm is formed by electroless plating at 80 to 90 ° C. It was formed as the outermost layer. After that, at room temperature
The pure water was washed for 10 minutes to form the barrier metal 5.

【0014】つぎに、バリアメタル5上にバンプを形成
する。具体例としては、半導体ウエハにバリアメタルの
部分のみが露出するような、厚さ0.05mm程度の金属マス
クを被せ、ハンダペーストを印刷法によって開口部に埋
め込むように塗布した。そののち、200 〜 240℃で約5
分間ハンダペーストを溶融させることにより、厚さが50
〜70μm程度のバンプを形成した。
Next, bumps are formed on the barrier metal 5. As a specific example, a semiconductor wafer was covered with a metal mask having a thickness of about 0.05 mm so that only the barrier metal portion was exposed, and a solder paste was applied by a printing method so as to be embedded in the opening. After that, at 200-240 ℃, about 5
50 minutes by melting the solder paste for
Bumps of about 70 μm were formed.

【0015】叙上の製法によれば、無電解メッキによっ
てバリアメタルの各層をボンディングパッド上にのみ密
着性がよく、しかも均一に成膜できるため、信頼性の高
いバリアメタル5を簡単にうることができる。このえら
れた半導体装置に対し、 175℃、 100時間の加熱試験を
実施したが機械特性、電気特性ともに問題なく、バリア
メタルの効果が確認された。
According to the above manufacturing method, each layer of the barrier metal can be adhered only on the bonding pad by electroless plating, and the barrier metal 5 can be uniformly formed. Therefore, the highly reliable barrier metal 5 can be easily obtained. You can The semiconductor device thus obtained was subjected to a heating test at 175 ° C. for 100 hours, and there was no problem in mechanical properties and electrical properties, and the effect of the barrier metal was confirmed.

【0016】また、本発明によれば金膜8の形成も他の
金属膜と同様の手順でできるため、専用の蒸着装置を必
要としない。
Further, according to the present invention, since the gold film 8 can be formed by the same procedure as that for other metal films, a dedicated vapor deposition device is not required.

【0017】なお、前記実施例では、ボンディングパッ
ド3の材料としてAl−Siを用いたが、本発明はこれ
に限定されるものではなく、アルミニウムなど電極膜と
して好ましい金属材料であれば、自由に選択することが
できる。
Although Al--Si is used as the material of the bonding pad 3 in the above embodiment, the present invention is not limited to this, and any metal material such as aluminum that is preferable for the electrode film can be freely used. You can choose.

【0018】[0018]

【発明の効果】本発明によれば、無電解メッキによって
バリアメタルを形成するため、各ボンディングパッドに
のみバリアメタルを形成でき、フォトレジスト工程の必
要がなく、簡単にバリアメタルを形成することができ
る。さらに、大量の半導体装置を半導体ウエハのままで
一括して無電解メッキを行うことができ、しかも、短時
間でバリアメタルを形成することができる。また、バン
プはスクリーン印刷などで形成できるため、短時間で行
え、大幅な製造コストの低減を達成することができる。
According to the present invention, since the barrier metal is formed by electroless plating, the barrier metal can be formed only on each bonding pad, and the barrier metal can be easily formed without the need for a photoresist process. it can. In addition, a large number of semiconductor devices can be collectively subjected to electroless plating on a semiconductor wafer as it is, and furthermore, a barrier metal can be formed in a short time. Moreover, since the bumps can be formed by screen printing or the like, the bumps can be formed in a short time, and a significant reduction in manufacturing cost can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製法の一実施例を説明す
るためのバンプ部分の断面説明図である。
FIG. 1 is a cross-sectional explanatory view of a bump portion for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention.

【図2】従来の半導体装置のバンプ部の断面説明図であ
る。
FIG. 2 is a cross-sectional explanatory diagram of a bump portion of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 3 ボンディングパッド 4 パッシベーション膜 5 バリアメタル 6 第1層 7 第2層 8 最外層 9 バンプ 1 Semiconductor Substrate 3 Bonding Pad 4 Passivation Film 5 Barrier Metal 6 First Layer 7 Second Layer 8 Outermost Layer 9 Bump

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板に半導体回路が形成され、該
半導体回路から外部導出用の電極膜が半導体チップの周
縁部に導出されてボンディングパッドが形成され、該ボ
ンディングパッド上に外部リードとの接続用のバンプが
設けられてなる半導体装置の製法であって、 前記ボンディングパッド上に無電解メッキ法によりバリ
アメタルを設け、該バリアメタル上にバンプを形成する
ことを特徴とする半導体装置の製法。
1. A semiconductor circuit is formed on a semiconductor substrate, an electrode film for external lead-out is led out from the semiconductor circuit to a peripheral portion of a semiconductor chip to form a bonding pad, and a bonding pad is connected to the external lead. A method of manufacturing a semiconductor device having bumps for use, wherein a barrier metal is provided on the bonding pad by electroless plating, and a bump is formed on the barrier metal.
【請求項2】 前記ボンディングパッドを1μm以上の
厚さのアルミニウムを主成分とする金属膜から形成し、
前記バリアメタルを設ける前に前記ボンディングパッド
表面をエッチングしてアルミニウムを活性化させること
を特徴とする請求項1記載の半導体装置の製法。
2. The bonding pad is formed of a metal film containing aluminum as a main component and having a thickness of 1 μm or more,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the surface of the bonding pad is etched to activate aluminum before the barrier metal is provided.
JP4291679A 1992-10-29 1992-10-29 Semiconductor device manufacturing method Expired - Fee Related JP2784122B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4291679A JP2784122B2 (en) 1992-10-29 1992-10-29 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4291679A JP2784122B2 (en) 1992-10-29 1992-10-29 Semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
JPH06140409A true JPH06140409A (en) 1994-05-20
JP2784122B2 JP2784122B2 (en) 1998-08-06

Family

ID=17772021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4291679A Expired - Fee Related JP2784122B2 (en) 1992-10-29 1992-10-29 Semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JP2784122B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199506A (en) * 1995-11-15 1997-07-31 Citizen Watch Co Ltd Method for forming bump on semiconductor chip
DE19616373A1 (en) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Forming galvanically deposited contact bumps for integrated circuits
US5989993A (en) * 1996-02-09 1999-11-23 Elke Zakel Method for galvanic forming of bonding pads
KR20010061775A (en) * 1999-12-29 2001-07-07 이수남 wafer level package and method of fabricating the same
US6689639B2 (en) 2001-11-15 2004-02-10 Fujitsu Limited Method of making semiconductor device
US6809020B2 (en) 2000-05-01 2004-10-26 Seiko Epson Corporation Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic device
JP2007506284A (en) * 2003-09-22 2007-03-15 インテル コーポレイション Conductive bump structure and manufacturing method thereof
US7378296B2 (en) 2003-02-25 2008-05-27 Kyocera Corporation Print mask and method of manufacturing electronic components using the same
US7579692B2 (en) 2000-09-04 2009-08-25 Seiko Epson Corporation Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument
US11824024B2 (en) 2019-05-13 2023-11-21 Fuji Electric Co., Ltd. Semiconductor module and method of manufacturing semiconductor module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63305532A (en) * 1987-06-05 1988-12-13 Toshiba Corp Forming method for bump
JPH02224336A (en) * 1989-02-27 1990-09-06 Nec Corp Manufacture of semiconductor device
JPH03225923A (en) * 1990-01-31 1991-10-04 Toshiba Corp Formation of bump

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63305532A (en) * 1987-06-05 1988-12-13 Toshiba Corp Forming method for bump
JPH02224336A (en) * 1989-02-27 1990-09-06 Nec Corp Manufacture of semiconductor device
JPH03225923A (en) * 1990-01-31 1991-10-04 Toshiba Corp Formation of bump

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199506A (en) * 1995-11-15 1997-07-31 Citizen Watch Co Ltd Method for forming bump on semiconductor chip
US5989993A (en) * 1996-02-09 1999-11-23 Elke Zakel Method for galvanic forming of bonding pads
DE19616373A1 (en) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Forming galvanically deposited contact bumps for integrated circuits
KR20010061775A (en) * 1999-12-29 2001-07-07 이수남 wafer level package and method of fabricating the same
US6809020B2 (en) 2000-05-01 2004-10-26 Seiko Epson Corporation Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic device
US7579692B2 (en) 2000-09-04 2009-08-25 Seiko Epson Corporation Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument
US6689639B2 (en) 2001-11-15 2004-02-10 Fujitsu Limited Method of making semiconductor device
US7378296B2 (en) 2003-02-25 2008-05-27 Kyocera Corporation Print mask and method of manufacturing electronic components using the same
US7638420B2 (en) 2003-02-25 2009-12-29 Kyocera Corporation Print mask and method of manufacturing electronic components using the same
JP2007506284A (en) * 2003-09-22 2007-03-15 インテル コーポレイション Conductive bump structure and manufacturing method thereof
JP2015167257A (en) * 2003-09-22 2015-09-24 インテル コーポレイション Compact electronic apparatus, formation method thereof, and system
US11824024B2 (en) 2019-05-13 2023-11-21 Fuji Electric Co., Ltd. Semiconductor module and method of manufacturing semiconductor module

Also Published As

Publication number Publication date
JP2784122B2 (en) 1998-08-06

Similar Documents

Publication Publication Date Title
KR100375460B1 (en) Method for preparing a conductive pad for electrical connection and conductive pad formed
JP4068293B2 (en) Rearrangement chip size package and manufacturing method thereof
US8230591B2 (en) Method for fabricating an electronic device substrate
EP0382080A2 (en) Bump structure for reflow bonding of IC devices
US5171711A (en) Method of manufacturing integrated circuit devices
JP3949505B2 (en) CONNECTION TERMINAL, ITS MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND ITS MANUFACTURING METHOD
TW200832641A (en) Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof
US20020014705A1 (en) Semiconductor device and manufacturing method of same
JP2004517498A (en) Cu pad / Cu wire bonded using self-passivating Cu alloy
JPH09199506A (en) Method for forming bump on semiconductor chip
JP2784122B2 (en) Semiconductor device manufacturing method
JP3648585B2 (en) Semiconductor device and manufacturing method thereof
US20010013651A1 (en) Semiconductor device and manufacturing method therefor
JP2000150518A (en) Manufacture of semiconductor device
JP3407839B2 (en) Method of forming solder bump for semiconductor device
JP2005109427A (en) Semiconductor device and its manufacturing method
TW200304176A (en) Semiconductor device and manufacturing method thereof
JP2000299339A (en) Semiconductor device and manufacture thereof
JP2005268442A (en) Semiconductor device and its manufacturing method
JP3506686B2 (en) Method for manufacturing semiconductor device
JP2006120803A (en) Semiconductor device and manufacturing method therefor
JP2633580B2 (en) Bump, bump forming method, and semiconductor element
JP2839513B2 (en) Method of forming bump
JP3297717B2 (en) Method for forming electrode of semiconductor device
JPH03177048A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees