KR960000051Y1 - Pla added connection line - Google Patents
Pla added connection line Download PDFInfo
- Publication number
- KR960000051Y1 KR960000051Y1 KR2019900017413U KR900017413U KR960000051Y1 KR 960000051 Y1 KR960000051 Y1 KR 960000051Y1 KR 2019900017413 U KR2019900017413 U KR 2019900017413U KR 900017413 U KR900017413 U KR 900017413U KR 960000051 Y1 KR960000051 Y1 KR 960000051Y1
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- pla
- connection line
- gates
- gate
- sum
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
내용 없음.No content.
Description
제 1 도는 종레의 PLA의 구조도1 is a structural diagram of PLA of the bell
제 2 도는 본 고안에 다른 PLA의 구조도이다.2 is a structural diagram of another PLA in the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
AND 1 ∼AND 4 : 앤드게이트 OR 1 ∼ OR 4 : 오어게이트AND 1 to AND 4: AND gate OR 1 to OR 4: Or gate
본 고안의 PLA(Programmable Logic Array)에 관한 것으로, 특히 연결선을 추가하여 기존의 PLA의 효율을 증가시킨 PLA에 관한 것이다.The present invention relates to a PLA (Programmable Logic Array) of the present invention, and more particularly to a PLA that increases the efficiency of the existing PLA by adding a connection line.
통상 PLA는 먼저 앤드게이트(AND GATE)를 통과하며 오어게이트(OR GATE)를 통해서 출력되게 된다. 각선의 교차부분은 현재 연결된 것이 아니라 연결가능한 지점을 나타낸다. 제1도에 도시한 PLA는 4개의 앤드게이트 (AND l ∼AND 4)와 4개의 오어게이트(OR 1 ∼ OR 4)로 구성되어, 함수 F=AB + BCD +AC를 구현하기 위하여 전기적으로 연결된 상태를 나타낸다.Normally, the PLA first passes through an AND gate and is output through an OR gate. The intersection of each line represents the connectable point, not the current connection. The PLA shown in FIG. 1 is composed of four end gates (AND 1 to 4) and four or gates (OR 1 to OR 4), and is electrically connected to implement the function F = AB + BCD + AC. Indicates the state.
그러나, 종래의 PLA는 곱들의 합을 구현하도록 되어 있으므로 합을 먼저 수행하는 경우에는 어려운 문제점이 있었다.However, since the conventional PLA is to implement the sum of the products, there is a difficult problem when performing the sum first.
예를 들어, 4개의 앤드게이트와 4개의 오어게이트로 구성된 PLA는 함수 F = AB +AC +AD +BD +CD를 구현하기에는 앤드게이트가 부족하므로, 상기 함수를 F = A (B + C +D) +BC + CD의 형태로 바꾸어 수행하여야 한다.For example, a PLA consisting of four endgates and four orgates lacks an endgate to implement the function F = AB + AC + AD + BD + CD, so the function F = A (B + C + D ) It should be changed to + BC + CD.
그러나, 구조상 합을 먼저 수행할 수 없으므로 상기 함수를 구현할 수가 없었다.However, since the structural sum cannot be performed first, the function cannot be implemented.
본 고안은 이와 같은 문제점을 해결하기 위한 것으로, 본 고안의 목적은 합을 먼저 수행할 수 있도록 부가적인 연결선이 마련된 PLA를 제공하는 것이다.The present invention is to solve such a problem, an object of the present invention is to provide a PLA provided with an additional connection line to perform the sum first.
이와 같은 목적을 달성하기 위한 본 고안의 특징은 다수개의 앤드게이트와 다수개의 앤드게이트 후단에 연결된 다수개의 오어게이트로 구성된 PLA회로에 있어서, 다수개의 앤드게이트의 사이에 마련되어 입력을 다수개의 오어게이트에 연결시키기 위한 적어도 하나의 제 Ⅰ연결선과, 다수개의 오어게이트의 출력측과 다수개의 앤드게이트의 입력단을 서로 연결시키기 위한 적어도 하나의 제 2 및 제 3연결선을 포함하는 PLA회로에 있다.In order to achieve the above object, a feature of the present invention is a PLA circuit composed of a plurality of AND gates and a plurality of OR gates connected to a plurality of AND gates, and is provided between a plurality of AND gates to provide inputs to a plurality of OR gates. The PLA circuit includes at least one first connection line for connecting and at least one second and third connection line for connecting the output side of the plurality of or gates and the input terminal of the plurality of AND gates to each other.
이하, 본 고안을 첨부도면에 의하여 상세히 설명한다.Hereinafter, the present invention will be described in detail by the accompanying drawings.
제 2 도는 본 고안에 다른 PLA의 1예로서 4개의 앤드게이트(AND 1∼ AND 4)와 4개의 오어게이트(OR 1∼OR 4)로 구성된 PLA에 연결선(CL 1∼CL 5)이 마련된 것을 나타낸다 즉 각각의 앤드게이트(AND 1∼AND 4)의 사이에는 연결선(CL 1∼CL 3)이 마련되어 오어게이트(OR 1∼OR 4)의 입력측에 연결되며, 오어게이트(OR 1∼OR 4)의 출력측이 연결된 연결선(CL 4)이 마련되어 앤드게이트(AND 1∼ AND 4)의 입력측과 연결되도록 이루어지며, 앤드게이트(AND 1∼AND 4)의 압력측이 연결된(CL 5)이 마련되어 오어게이트(OR 1∼ OR 4)의 출력측과 연결되도록 구성되어 있다.FIG. 2 shows that the connection lines CL 1 to CL 5 are provided on a PLA composed of four AND gates (AND 1 to AND 4) and four or gates (OR 1 to OR 4) as one example of another PLA according to the present invention. That is, connecting lines CL 1 to CL 3 are provided between the respective AND gates AND 1 to AND 4, and are connected to the input side of the OR gates OR 1 to OR 4, and the OR gates OR 1 to OR 4. Is connected to the input side of the AND gate (AND 1 to AND 4) provided with the connection line (CL 4) connected to the output side of, and the pressure side of the AND gate (AND 1 to AND 4) is connected (CL 5) is provided It is configured to be connected to the output side of (OR 1 to OR 4).
이렇게 구성된 PLA회로는 합을 먼저 수행할 수 있게 된다. 예를 들어, 이전에 설명한 바와 같은 함수 F = A(B + C + D) +BC +CD는 제 2 도에 나타낸 점과 같이 연결하면 간단히 구현할 수 있게 된다.The PLA circuit configured in this way can perform the sum first. For example, the function F = A (B + C + D) + BC + CD as previously described can be easily implemented by connecting as shown in FIG.
즉, 연결선(CL l)에 의해 입력(B)이, 연결선(CL 2)에 의해 입력(C)이, 연결선(CL 3)에 의해 입력(D)이 오어게이트(OR 1)를 거치게 되고, 이 오어게이트(OR 1)의 출력(B + C + D)이 연결선(C 14, C 15)에 의하여 앤드게이트(AND 1)의 입력측에 인가되어 입력(A)와 곱이 수행된다.That is, the input B passes through the OR gate 1 by the connection line CL 1, the input C through the connection line CL 2, and the input D through the connection line CL 3. The output B + C + D of the or gate OR 1 is applied to the input side of the AND gate AND 1 by the connection lines C 14 and C 15 to perform a multiplication with the input A.
또한, 이러한 앤드게이트(AND 1)의 출력 A (B +C +D)과 앤드게이트(AND 2)의 출력(BC)과 앤드게이트(AND 3)의 출력(CD)이 오어게이트(OR2)를 통하게 되어 원하는 합수 F= A ( B + C+ D)+ BC +CD를 구현할 수 있게 된다.In addition, the output A (B + C + D) of the AND gate AND 1, the output BC of the AND gate AND 2, and the output CD of the AND gate AND 3 are connected to the OR gate OR2. This allows us to implement the desired sum F = A (B + C + D) + BC + CD.
이상 설명한 바와 같이, 본 고안에 따르면 기존의 PLA에 부가적인 연결선을 마련하는 것에 의하여 합이나 곱중 어느 것이나 먼저 수행할 수 있게 되어 PLA의 수행능력의 중대 효과를 얻을 수 있다.As described above, according to the present invention, by providing an additional connection line to the existing PLA, any one of a sum or a product can be performed first, thereby obtaining a significant effect of the performance of the PLA.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019900017413U KR960000051Y1 (en) | 1990-11-13 | 1990-11-13 | Pla added connection line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019900017413U KR960000051Y1 (en) | 1990-11-13 | 1990-11-13 | Pla added connection line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920010634U KR920010634U (en) | 1992-06-17 |
| KR960000051Y1 true KR960000051Y1 (en) | 1996-01-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019900017413U KR960000051Y1 (en) | 1990-11-13 | 1990-11-13 | Pla added connection line |
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| Country | Link |
|---|---|
| KR (1) | KR960000051Y1 (en) |
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1990
- 1990-11-13 KR KR2019900017413U patent/KR960000051Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920010634U (en) | 1992-06-17 |
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