JPS6211316A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To realize both stable circuit operation and high speed operation by separating a latch circuit and an output circuit. CONSTITUTION:The latch circuit 1 consists of NAND gates A, B and NAND gates C, D are added in parallel with the gates A, B and the output terminals of the gates C, D are used as the outputs Q, Q' of an FF circuit. Thus, the output terminals 11, 12 of the circuit 1 and the outputs Q, Q' are separated and the adverse effect on the FF operation due to the feedback of the state of the outputs Q, Q' to the circuit 1 is avoided. Further, only one gate stage is enough from the set terminal to the Q output so as to speed up the operation.

Description

[Detailed Description of the Invention] Daily Income Summary] The flip-flop circuit of the present invention includes a cross-over circuit,
The cross-crossing circuit performs the logic function of a flip-flop, and the output is taken from the logic gates connected in parallel to ensure stable operation. The aim is to improve speed and speed.

[Industrial application field]

The present invention relates to a method of configuring a flip-flop circuit using a gate circuit.

[Conventional technology]

FIG. 7 shows an example of a conventional flip-flop circuit using cross-linked gate circuits.

In this circuit, the output terminal of each gate is connected to the input terminal of the other gate circuit, so if the output terminal drops even momentarily below the input threshold voltage of the gate circuit, the flip-flop will be inverted. In other words, if the Q terminal is shorted to, for example, ground potential when the Q output is "high", it will be the same as if there was a reset input to the gate circuit on the B side, the flip-flop would be inverted, and the Q output would become "low". ” 9 stone output is “high”. This kind of situation occurs not only in abnormal cases such as short circuits of output terminals, but also in
If the output signal line is routed for a long time for a subsequent circuit, problems can occur relatively easily due to signal reflection or induction from other circuits.

If the operation of the circuit changes even from the output terminal in this way, there is a risk that the operation of the entire circuit including this circuit may become abnormal.

In addition, in order to prevent such abnormal operation, if the buffer 2 is connected to the cross-over circuit as shown in Fig. 8,
Due to the signal delay caused by the buffer 2, some of the high speed of circuit operation is lost.

The timing diagram in FIG. 9 is a diagram showing the time relationship between the signals in FIGS. 7 and 8 above. Assuming that the delay time of each element is almost equal and that this is td, the circuit in FIG. ,
The delay of the Q output with respect to the cent input is only one gate stage delay tdL, but in the circuit of FIG.
A stage delay occurs. The delay of Q output with respect to reset is also
In the circuit of Fig. 7, there is only td, that is, one stage, whereas
In the circuit of FIG. 8, a delay equivalent to 3Xtd111, or three stages, also occurs.

[Problem that the invention seeks to solve]

As mentioned above, conventional flip-flop circuits have the risk of the circuit being reversed depending on the state of the output, and if this risk is removed, the high-speed performance of the circuit will be impaired.

An object of the present invention is to provide a method for configuring a flip-flop circuit that operates at high speed and is not affected by subsequent circuits by separating the gate circuit that makes up the cross-over circuit from the output gate circuit. It is about providing.

[Means for solving problems]

The flip-flop circuit of the present invention shown in FIG. Logic gates C and D are connected in parallel to each other (the figure shows an example in which they are connected to both). The cross-crossing circuit 1 performs the logic function of a flip-flop, and the output is the logic gates C and D connected in parallel.
It is configured to be retrieved from.

In the flip-flop circuit having the above configuration, as the logic gates A and B constituting the cross-crossing circuit l, an AND circuit with inversion, ie, a NAND circuit, or an OR circuit with inversion, ie, a NOR circuit, is used. Logic gates C and D connected in parallel are logic games) A and B are NAND
In the case of a circuit, a NAND circuit or an AND circuit is used, and if logic gates A and B are NOR circuits, a NOR circuit or an OR circuit is used.

[For production]

Since the logic gate that performs the logic function and the logic gate that takes out the output are separated and connected in parallel, malfunctions caused by abnormalities on the output side being fed back to the input side are prevented, and input/output Since the number of stages in between does not increase, the delay time does not increase and high-speed operation is possible.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the first embodiment of the present invention shown in FIG.
NAND gates C and D are added in parallel with D gates A and B, and the output terminals of these added gates C and D are the output terminal Q of the flip-flop circuit.

This is an example of Q.

With this configuration, the output terminals 11 and 12 of the crossing circuit 1 that controls the logic function and the output terminal Q of the circuit
, Q are separated from each other, the states of the output terminals Q and Q are fed back to the cross-crossing circuit 1, and the flip-flop operation is not affected and becomes stable.

In addition, the number of gate stages from the set terminal to the Q output is one, so that high-speed operation can be achieved.

Furthermore, it is also possible to drive a large number of gates by using output NAND gates (C and D) with large current capacities.

FIG. 2 is a diagram showing the configuration of a second embodiment of the present invention, and this embodiment is an example in which only one AND gate C is provided as an additional gate.

In this embodiment as well, since the number of stages from the set terminal to the Q output is one, the delay is reduced.

When a NAND gate is used as a logic gate in this way, the additional gate for output may be an AND gate, or the number of additional gate for output may be only one. The effects of this embodiment are the same as those of the first embodiment.

FIG. 3 is a diagram showing the configuration of a third embodiment of the present invention.
This is an example using ND gates E and F connected in parallel.

In this way, by using two types of logic gates of the same type as the logic gates constituting cross-crossing circuit 1 as output expansion gates, two sets of outputs Q+, Ql,
C2, C2 can also be obtained.

Furthermore, in this embodiment as well, the number of stages from the set end to Ql and the output end is one, so high-speed operation is not impaired.

A fourth embodiment of the present embodiment shown in FIG. 4 is an example in which a three-state gate C is used as an additional gate, and the output terminal can be controlled.

FIG. 5 shows a fifth embodiment of the present invention, in which an additional gate and an A
This is an example of a circuit that also serves as an ND gate circuit. With this circuit, a high-speed gate circuit using flip-flop output can be realized.

In all of the five embodiments described above, examples have been given in which the cross-crossing circuit 1 is composed of NAND gates. However, it is also possible to use gates other than NAND gates to configure this cross-over circuit 1.

FIG. 6 shows a sixth embodiment in which the cross-over circuit 1 is constructed using NOR gates A and B instead of NAND gates. In this case, NOR gates E and F or OR gate C2D are used as additional output gates.

The effects of this embodiment are the same as those of the first to fifth embodiments.

As explained in the first to sixth embodiments above, the present invention can be implemented with various modifications.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to simultaneously stabilize and speed up the operation of a flip-flop circuit.

[Brief explanation of drawings]

1 to 6 are diagrams showing the configurations of the first to sixth embodiments of the present invention, FIGS. 7 and 8 are diagrams showing the configuration of conventional flip-flop circuits, and FIG. 9 is a diagram showing the configurations of conventional flip-flop circuits. FIG. 3 is a timing diagram of a flip-flop circuit. In the figure, 1 is a cross-crossing circuit, A and B are logic gates constituting the cross-crossing circuit 1, and C and D. E and F are logic games "1" that constitute the output expansion gate 2.
・7 Thatch - Figure 3, Figure 4, Figure 5, Figure 6, Figure S

Claims (1)

[Claims] Two AND gate circuits [or OR gate circuits] (
A, B) A cross-over circuit 1 configured such that the output of one is the input of the other, and the two AND gate circuits [
or OR gate circuit] (A, B) and an AND gate circuit [or OR gate circuit] (C, D) connected in parallel to at least one of the gate circuits (A, B) connected in parallel. A flip-flop circuit characterized in that the output terminals of C and D) are the output terminals of the circuit.