JPH0556687B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to complementary MOS integrated circuits, particularly to output circuits.

[Conventional technology]

Conventionally, in this type of output circuit, as shown in FIG. 3, an input signal from an input terminal 1 is received by a gate circuit 14 made up of one inverter, and an output signal is generated by one inverter 15 driven by the output of the gate circuit 14. The configuration is such that the output is output from the output terminal 2, and each inverter is a complementary type inverter in which a P-channel MOSFET and an N-channel MOSFET are connected in series.

[Problem that the invention seeks to solve]

When driving a capacitive load using the conventional output circuit described above, the larger the current drive capability of the MOSFET that constitutes the inverter 15 in the output stage, the faster the rise and fall times of the output waveform become. For this reason,
Usually constitutes the inverter 15 in the output stage.
The gate width of the MOSFET was increased to obtain steep rises and falls of the output waveform. however,
When driving a capacitive load with a large current to obtain steep rises and falls, ringing occurs in the rise and fall portions of the output waveform, resulting in malfunction of the entire circuit.

[Means for solving problems]

According to the present invention, the first logic circuit receives first and second input signals, performs predetermined logic processing on them, and outputs the result, and has a first logic threshold. , a logic circuit that receives the first and second input signals, performs the same logic processing on them as the first logic circuit, and outputs the result, the second logic circuit being lower than the first logic threshold; a second logic circuit having a logic threshold of; a first inverter receiving an output of the first gate circuit;
a second inverter receiving the output of the second gate circuit, the outputs of the first and second inverters are commonly connected to drive a load, and the driving capacity of the first and second inverters is An output circuit characterized in that the sum of the values is set to a desired value is obtained. That is, for example, the logic threshold of the second gate circuit receiving the input signal is both set lower than the logic threshold of the first gate circuit receiving the input signal. Therefore, in response to the input signal, the second output inverter first supplies the output to the capacitive load, and then the first output inverter also supplies the output to the capacitive load,
At this point, the desired output drive capability is obtained. Therefore, in the initial stage when the output is applied to the capacitive load, the output current is small, the rise and fall of the output voltage becomes smooth, and ringing can be prevented from occurring.

Next, as a preparation before explaining the present invention, FIG. 1 shows an example in which the conventional output circuit shown in FIG. 3 is improved. The outputs of inverter 4 and inverter 6 are connected to output terminal 2 in parallel. The logic threshold of inverter 3, which drives inverter 4, is set lower, and the logic threshold of inverter 5, which drives inverter 6, is set higher, and these are set with a difference. The inputs of these inverters 3 and 5 are both connected to the input terminal 1.

When the input to the input terminal 1 starts to change from low to high, it first reaches the threshold voltage of the inverter 3 and the output of the inverter 3 is inverted. However, since the threshold voltage of the inverter 5 has not been reached at this time, the output of the inverter 5 is not inverted. In other words, since the output terminal 2 and subsequent parts are driven only by the inverter 4, the rise is gradual. However, when the input reaches high, the threshold voltage of the inverter 5 is reached and the output is inverted. Therefore, since inverter 4 and inverter 6 operate simultaneously, there is no change in the original driving capability of the output circuit.

At this time, when the power supply voltage is 4.5V and the difference in threshold voltage between inverter 3 and inverter 5 is 1.0V,
The rise time is 1.0 [ns] slower than before, which prevents ringing.

〔Example〕

FIG. 2 is an equivalent circuit diagram of an embodiment of the present invention.
Inverter 11 and inverter 13 are connected to output terminal 9.
are connected in parallel. The NAND gate 10 that drives the inverter 11 and the NAND gate 12 that drives the inverter 13 are similar to the first embodiment.
The logical threshold values are set differently. Each NAND
Input signals are applied to gates 10 and 12 from input terminals 7 and 8, respectively.

In this embodiment, the gate circuit that drives the output inverter has a logic function, which has the advantage of preventing ringing and realizing logic functions such as a data selection function.

〔Effect of the invention〕

As explained above, in the present invention, in an output circuit that performs logic processing on two input signals and then outputs the result, this logic processing is performed within the output circuit, and the logic circuit is By adding two output terminal drive circuits to form two output terminal drive circuits and setting these logic circuits to different logic thresholds, you can arbitrarily control the rise and fall times of the output waveform to create ringing in the output waveform. This has the effect of preventing the occurrence of At this time, since output currents are supplied to the output from a plurality of inverters, the final driving ability of the output circuit does not change. As described above, by using the output circuit of the present invention in the output stage of a high-speed integrated circuit, it is possible to solve problems such as ringing due to high drive capability.

Furthermore, the present invention has the effect that an increase in the number of circuit elements can be suppressed to a minimum when preventing ringing and the like.

[Brief explanation of drawings]

1 and 2 are equivalent circuit diagrams showing embodiments of the present invention, and FIG. 3 is an equivalent circuit diagram showing a conventional output circuit. 1, 7, 8... Input terminal, 2, 9... Output terminal, 3, 4, 5, 6, 11, 13, 15... Inverter, 10, 12... NAND gate.

Claims (1)

[Claims] 1. A first logic circuit that receives first and second input signals, performs predetermined logic processing on them, and outputs the result, and has a first logic threshold; A logic circuit that receives a second input signal, performs the same logic processing on these as the first logic circuit, and outputs the result, and has a second logic threshold that is lower than the first logic threshold. a first inverter receiving an output of the first logic circuit; and a second inverter receiving an output of the second logic circuit; An output circuit characterized in that the outputs of the first and second inverters are commonly connected to drive a load, and the sum of the driving capacities of the first and second inverters is set to a desired value.