JPS61167220A - Signal output circuit - Google Patents

Abstract

PURPOSE:To suppress the adverse effect due to a transient current in driving an external load by synthesizing drive currents from plural terminal drive circuits having a different time response to same output information. CONSTITUTION:Transistors (Trs) Q13, Q14 and Q17, Q18 form respectively terminal drive circuits and outputs are connected in parallel. When a voltage on a signal line 11 changes from H to L, buffers each comprised of Q11, Q12 and Q15, Q16 output respectively an inverting signal. When the buffer of the Q11, Q12 has a higher inverting threshold value than the buffer of the Q15, Q16, the Q14 is turned on earlier than the Q18 and then the Q18 is turned on. As a result, the synthesized waveform of the drive currents flowing to the Q14, Q18 is a trapezoidal form. Then the peak value of the drive current is decreased, the time change in the current is decreased to suppress the adverse effect of the transient current.

Description

DETAILED DESCRIPTION OF THE INVENTION A) Field of Industrial Application The present invention relates to a signal output circuit, particularly to a digital signal output circuit for semiconductor integrated circuits.

(2) Prior Art When a digital signal output circuit of a semiconductor integrated circuit drives an external load, particularly a capacitive load or an actance load, a transient current flows into the signal output circuit through the output terminal. This current flows into the power supply wiring of the integrated circuit and causes potential fluctuations in the power supply wiring. As a result, the margin for one circuit operation decreases, and in severe cases even malfunctions occur. In order to solve this problem, one method is usually adopted, for example, by widening the width of the power supply wiring within the integrated circuit to lower the impedance.

As the area of the integrated circuit increases, the length of the power supply wiring becomes longer, which requires a wider wiring width, which tends to impede higher density of the integrated circuit.

There are also methods of suppressing the instantaneous current by, for example, lowering the driving ability of the output circuit or starting driving slowly, but these methods generally have the disadvantage that the operating speed deteriorates.

The aim is to realize a signal output circuit that suppresses noise and does not interfere with high-speed operation.

(b) Means for Solving the Problems The signal output circuit of the present invention includes a plurality of terminal drive circuits connected in parallel to which common output information is given and coupled to the same output terminal, and each terminal for the output information The response times of the drive circuits are made different.

(E) Function According to the present invention, drive currents from a plurality of terminal drive circuits that respond differently over time to the same output information are combined and supplied to the same output terminal.

The drive current waveform can be shaped into a nearly trapezoidal shape. This reduces the peak value of the drive current, reduces the time change in the current, suppresses the adverse effects of transient current, and allows this drive current to flow from the bottle to the external circuit in a short time, achieving high-speed operation. becomes.

(F) Embodiment An embodiment of a signal output circuit according to the present invention will be described in comparison with a conventional example. For the sake of explanation, complementary type MO8 (0MO8)
An example of a circuit will be shown, but the present invention is not limited to 0MO8, but can also be applied to digital signal output circuits composed of P-channel type, n-channel type, and even bipolar transistors.

FIG. 3(a) is an example of a conventional signal output circuit.

In the figure, C311 is a signal line that supplies output data to the signal output circuit, C34 is an output terminal of the integrated circuit, and C31 is an external capacitive load. Also, Ql is P channel MO8F
ET, Q2 is n-channel/l/MO8FET and QI
Q2 constitutes a terminal drive circuit for <S output.

On the other hand, FIG. 3(1)) shows the voltage Vin f(a) on the signal line r311 and the terminal C during the operation in FIG. 3(lL).
(3) Electrician II! FIG. 2 is a conceptual diagram of the time t shown in FIG.

Now, the signal line C31) in FIG. 6(a)! Figure 83 (1)
As shown in (a) of ), when the signal changes from LOWL/bell to Htgh level.

Transistor Q1 is turned off and Q2 is turned on.

At this time, the charge accumulated in the external capacitive load flows into the terminal C33 via the reactive load C33.If Q2 changes quickly from off to on, this current will flow into the third terminal.
As shown in (b) of Figure (1')), a sharp change occurs, causing the potential fluctuation of the power supply wiring as described above.

FIG. 1(a) shows an example of a signal output circuit according to the present invention. fIu and f121 in Figure 1 are a signal line and an output terminal, respectively, and have the same functions as cllJ and o in Figure 3, respectively.

Note that the external capacitive load is omitted in FIG. 1 and FIG. 182, which will be described later.

In FIG. 1, qz, QlB, Q15. Q17 is a P-channel MO8FET, Ql 2. Ql 4, Q16. Q
1B is n-channel A/MO8FKT.

Q1 black, Q14 and Q17. Q18 each constitute a terminal drive circuit, and their outputs are connected in parallel.

Qll, Ql 2 and Q15. Each Q16 constitutes an inversion buffer, but the inversion thresholds for changes in the signal line aυ are designed to be different.

Figure 1 (kl) also has the same signal line 11 as 131ffi (b).
The voltage vin of No. 11 is shown in (c), and the current change at the terminal fill is shown in (c).

In addition, the current component flowing from the terminal (13 to Q14 (E)
The current component flowing into 018 is shown in (to). These combined currents are shown in (g).

When the voltage of the signal line aD in Fig. 1 [) changes from High to LOW as shown in Fig. 1 (011), Ql
l.

Q12 and Q15. Each of the Q16 buffers outputs an inverted signal. Here, Ql 1. The buffer of Ql 2 is Q
15. Given a higher inversion threshold than the buffer in Qll, Q14 will turn on earlier than Q18, followed by Q18.

As a result, as shown in (1) in the figure, the terminal current of the output terminal 0z first flows to Q14, and then begins to flow to Q18 as well.

Here, 1. For example, Q14 has a composite waveform that is approximately trapezoidal.
The driving ability of the combined current of Ql6 and Ql6 is Q2 in Figure @3.
If configured so that the current drive capacity is equivalent to that of Q14
The transient current when only is turned on can be suppressed to be smaller than in the case of the vIs diagram. On the other hand, when QlB reaches the on state, the external container has already been discharged to some extent by Q14, so no steep transient current is generated. on the other hand.

Q94. When both QlB are on, it has the same current driving capability as Q2 in Figure 3, so the signal output delay compared to Figure 3 should be limited to the period from when Q14 turns on to when Q18 turns on. I can do it. That is, one composite waveform has a substantially trapezoidal shape as shown in (g) of the figure (to).

FIG. 2 is a 182 embodiment of the invention. 12n, ix
a is '@C in Figure 3 (same as 11C421,
C21 is P channel MO8FET, C22, C25 are n
Channel MO8FET. (to) is a resistor, (2a is a capacitor, and constitutes a delay circuit. This delay circuit may be configured in any manner, such as a delay circuit using an OR buffer or a delay circuit.

In Fig. 2, when the signal line 12DiLo1g is changed to Hlgh, C22 turns on first, then C23)C4
) QiJM turns on after a delay time. Even with this circuit configuration? The same effect as the one shown in Figure @1 can be obtained.

Now, in the explanation of 5 and above, MO8F on the n-channel side
The effect of the present invention on the transient current that occurs when the BT is turned on has been discussed, but in the embodiment of $1 factor, lI''
i, MO8FFi'['Qt&,Q17 on the P channel side
A similar effect can be expected when the transistor is turned on, and therefore when a transient current flows out.

(f) Effects of the Invention The signal output circuit of the present invention is divided into a plurality of terminal drive circuits and connected in parallel, so that each of the divided terminal drive circuits has a different time response to the same output information. This has the effect of reducing the maximum value of the current flowing into the signal output circuit, and on the other hand, by operating with a flattened drive capability within a short time, the signal delay Mffi caused by the output circuit itself can be kept to a small value.

Moreover, in order to actually realize the present invention, it is only necessary to add a small number of circuits and divide the signal output circuit, and the integration density of the integrated circuit is hardly reduced.

Therefore, by applying the present invention to the output circuit of an integrated circuit, the width of power supply wiring within the integrated circuit can be significantly increased.

Transient current in the signal output circuit can be suppressed without causing significant signal delay.

[Brief Description of the Drawings] Figure 1 (!L) and Ch) are circuit diagrams showing one embodiment of the signal output circuit of the present invention and their signal waveform diagrams, and Figure 2 is a diagram of another embodiment of the signal output circuit of the present invention. Circuit diagram of the embodiment, FIG. 3(a). and c'b) are a circuit diagram of a conventional circuit and a signal waveform diagram. An round on...signal line, C3 (2 IC (three peak output terminals, Q...transistor).

Claims (1)

[Claims] 1) A plurality of parallel-connected terminal drive circuits to which common output information is given are coupled to the same output terminal, and the plurality of terminal drive circuits have approximately the same response time for each output information. A signal output circuit characterized by having mutually different transient delay time ranges. 2) The signal output circuit according to claim 1, wherein the plurality of terminal drive circuits are set with mutually different threshold values for common output information.