JPH02109421A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To suppress a potential fluctuation of a power voltage lower by setting a charging transistor(TR) in the nonconducting state sequentially at a prescribed time interval and setting a discharge TR in the nonconducting state sequentially at a prescribed time interval. CONSTITUTION:An input signal is sequentially supplied to each gate of photoelectric MOS TRs TP7, TP8 to set the TRs in the conductive state sequentially. Simultaneously, an input signal is supplied sequentially to each gate of discharge MOS TRs TN13, TN14 to set them to the conductive state sequentially. When an output goes to an H level, a sudden increase in a VCC current is not caused and when the TRs TN13, TN14 are turned off, no sudden decrease in the VSS current is not caused. Moreover, the TRs TN13, TN14 are set conductive sequentially. Simultaneously, the TRs TP7, TP8 are set nonconductive sequentially. Thus, when the output goes to an L, the sudden increase in the VSS current is not caused and when the TRs TP7, TP8 are turned off, the sudden decrease in the VCC current is not caused.

Description

[Detailed description of the invention]

[Object of the Invention (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and particularly to an output buffer circuit thereof. (Prior Art) Conventionally, an output circuit in a semiconductor integrated circuit device has a groove bottom as shown in FIG. 6, for example. In FIG. 6, 11 to 14 are P-channel type MOS transistors Ql, Q3 . Q5゜Q7, and N
Channel type MOS transistor Q2. Q4. Q6. Q
A signal D1 from an internal circuit (not shown) is supplied to the gate of a P-channel charging MO3I-transistor Q9 via inverters 11 and 1.2, and is supplied to the gate of a P-channel charge MO3I transistor Q9 via an inverter 13.14. Channel type discharge MO9) is supplied to the gate of transistor QIO. MOS transistor Q9. QICI is connected in series between the power supply VCC and the ground point Vss, and the output signal D out is obtained from the connection point between these MOS transistors Q9 and QIO. Next, in the above configuration, FIG. 7(a). The operation will be explained with reference to (b). The figure (a) is
The waveform of each signal is shown when the signal D1 from the internal circuit changes from the "L" level to the "H" level. Figure (b) shows the waveform of each signal when the signal D1 changes from the "H" level to the "L" level. The waveforms of each are shown. As shown in FIG. 7(a), when the signal D1 from the internal circuit rises from the 'L° level to the 'H' level at time t1, the output D2 of the inverter 11 rises from the 'H' level to the 'L2' level at time t2. level starts to change, and at time t3, inverter 1
The output D4 of No. 3 also begins to change from the "H" level to the "L" level. At time t3 when the output D2 of the inverter 11 becomes lower than the circuit threshold of the inverter 2, the output D3 of the inverter 12
rises from the "L" level to the "H" level. As a result, the charging MOS transistor Q9 is turned off. Also, at time t4 when the output D4 of the inverter 13 becomes lower than the circuit threshold of the inverter 14, the output of the inverter 14 D5 rises from the "L" level to the "H" level. Therefore, the discharge mMOS transistor QIO is turned on, and the output signal D out is discharged from the "H2 level" to the "L" level at time t4. As shown in the figure, a large peak current flows between times t4 and t5 when the output signal D out is inverted. On the other hand, as shown in FIG. 7(b), when the signal D1 from the internal circuit falls from the 1H" level to the 'L' level at time t1, the output D4 of the inverter 13 falls from the 'L' level at time t2. At time t3, the output D2 of the inverter 11 also begins to change from the L level to the H level. At time t3, when the output D4 of the inverter 13 becomes higher than the circuit threshold of the inverter 14, ]4 output D5
When the voltage falls from “H” level to “L” level, discharge ~1
The 0S transistor QIO is turned off. Furthermore, at time t4 when the output D2 of the inverter 11 becomes higher than the circuit threshold of the inverter 12, the output D3 of the inverter 12 falls from the "H" level to the "L" level.As a result, the charging MOS transistor Q9 is turned on. , the output signal D out is charged from the "L" level to the 'H' level at time t4. This output signal D 0LIt
is reversed at time t4. As shown in the figure, a large peak current flows during t5. Incidentally, the final stage transistor in the output buffer circuit is generally designed to allow a large current to flow therein so that an external load capacitance of, for example, about 1009F can be charged and discharged in a short time. That is, in the circuit of FIG. 6, the discharge MOS transistor QIO is designed to allow a large current to flow so as to discharge the external load capacitance in a short time. For this reason,
When the discharge MOS transistor QIO changes from an off state to an on state, a large current flows, and the current increases rapidly, generating self-noise that causes circuit malfunction. Similarly, the charging MOS transistor Q9 is designed to allow a large current to flow in order to charge the external load capacitance in a short time, and a large current flows when the charging MO5) transistor Q9 changes from the off state to the on state. The disadvantage is that the current increases rapidly and generates self-noise that can cause circuit malfunction. As mentioned above, conventional output buffer circuits are designed to allow large currents to flow in order to charge and discharge large external load capacitances in a short period of time in order to increase their response speed. The disadvantage is that sometimes the current increases rapidly, generating self-noise and causing circuit malfunction. In order to eliminate such drawbacks, an output buffer circuit that can suppress the sudden increase in current and prevent the generation of self-noise that causes circuit malfunction is proposed. proposed by. This special application was made in 1986. The output buffer circuit according to No. 63214 includes a plurality of charge MoS transistors and discharge Mo3I transistors, and supplies the output of a first delay circuit that sequentially delays an input signal to each gate of the plurality of charge MOS transistors. and sequentially set the conduction state to multiple discharge MOs.
The output of a second delay circuit that sequentially delays an input signal is supplied to each gate of the S transistor, so that the gates of the S transistors are sequentially turned on. Also, 1st. The second delay circuit simultaneously transmits an input signal that makes the charge MOS transistor and the discharge MOS transistor non-conductive without delay, and simultaneously makes the plurality of charge MOS transistors or the plurality of discharge MOS transistors non-conductive. Configured to set. In the above configuration, when the output signal is inverted, the plurality of charge MOS transistors are sequentially turned on to set the output node to the ゛H° level, and the plurality of discharge MOS transistors
S) The transistors become conductive one after another and the output node becomes “
Since the L2 level is set, a sudden increase in current does not occur when the output is inverted. Further, since the non-conducting signal is not delayed, there is no risk of a through current flowing directly from the power supply VCC to the ground point vSS via the charging MO8) transistor and the discharging MOS transistor. Therefore, there is no need to slow down the speed compared to the conventional circuit to take measures against through current. In the output buffer circuit according to the above Japanese Patent Application No. 61-63214, as shown in FIG.
CM consisting of channel type Mo3) Lannostar Q12
OS inverter 15, P-channel type MOS transistor Q13, and N-channel type MOS transistor Q
The signal is supplied to a CMOS inverter 16 consisting of 14. The output of the inverter 15 is a P-channel type MOS transistor Q15 and an N-channel type MoS transistor Q1.
6, one end of which is connected to the voltage [Vc
P-channel type MOS transistor Q1 connected to c
7 and the gate of an N-channel MOS transistor Q18, one end of which is connected to the other end of the Mo5) transistor Q17.
8.19 to the gate of an N-channel MOS transistor Q19 connected between the other end of the MOS transistor 018 and the ground point Vss. MOS transistor Q17. Q18 and Q19 operate as an inverter 20 that performs a delay operation only when outputting an "L" level. The output of the inverter 17 is supplied to the gate of a P-channel charge transistor Q20, one end of which is connected to the power supply Vcc. The output of the inverter 20 from the connection point between the MOS transistors Q17 and 018 is a P-channel charging Mo8F whose one end is connected to the power supply VCC.
't is supplied to the gate of resistor Q21. Mo8) transistor Q20. The other ends of Q21 are commonly connected. The output of the inverter 16 is a P-channel type MOS transistor Q22 and an N-channel type MOS transistor 02.
CMOS inverter 21 consisting of 3, one end is the ground point V
N-channel MOS transistor Q connected to SS
24 and the gate of a P-channel type Mo5) transistor Q25, one end of which is connected to the other end of this MOS transistor Q24. It is supplied to the gate of a P-channel type MOS transistor Q26 connected therebetween. MOS) transistor Q24. Q25゜Q26 operates as an inverter 24 that performs a delay operation only when outputting the "H° level. The output of the inverter 21 is connected to the ~10Sh transistor Q20.
．． It is supplied to the gate of an N-channel discharge transistor Q27 connected between the common connection point on the other end side of Q21 and the ground point Vss. MOS transistors Q24 and 025
The output of the inverter 24 from the connection point with M
N-channel discharge MOS connected between the common connection point on the other end side of OS transistors Q20 and Q21 and the ground point VSS
It is configured to be supplied to the gate of transistor Q28. Next, in the above configuration, FIG. 9(a). The operation will be explained with reference to FIG. 10(b) and FIGS. 10(a) and 10(b). FIG. 9(a) shows the signal D1 from the internal circuit.
9(b) shows the output of the conventional circuit and the output buffer circuit according to the above patent application No. 61-63214 at this time. The current waveforms are shown in comparison. Also, Figure 10 (
10(a) shows the waveform when the signal D1 changes from the "H" level to the "L" level, and FIG. 10(b) shows the waveform of the conventional circuit at this time and the output buffer circuit according to the above-mentioned Japanese Patent Application No. 61-63214. The waveforms of the output currents are compared and shown. As shown in FIG. At time t2, the output D2 of the inverter 15 begins to change from the 'H° level to the 'L' level, and at time t3, when the output D2 of the inverter 915 becomes lower than the circuit threshold of the inverter 1720, the output D3. D4 begins to change from the "L" level to the "H2 level".As a result, the transistors Q20 and Q2] are simultaneously turned off.At the next time t4, the output D5 of the inverter 16 changes from the 'H2 level. The time when the output D5 of this inverter 16 starts to change to "L" level and becomes at higher than the circuit threshold of the inverter 21.24.

[5, these outputs D6.
D7 begins to change from the "L" level to the "H" level. At this time, since the signal D5 is delayed by the inverters 22 and 23, the MOS transistor Q26 of the inverter 24
The output of this inverter 24 slowly rises to the "H" level. Therefore, first, the output of the inverter 21 causes the discharge MOS
Transistor Q27 is turned on (time t5), and discharge MOS transistor Q28 is turned on at time t7. Therefore, the output signal D out becomes H' at time t5.
It begins to fall slowly from the level to 'L level, and reaches L'L level at time t8 after a predetermined time has elapsed from time t7. Time t5. when this output signal Dout is inverted. The current during t8 has a gentle slope as shown in FIG. 9(b), and no sudden increase in current occurs. On the other hand, as shown in FIG. 10(a), when the signal D1 from the internal circuit falls from the "H" level to the "L" level at time t1, the output D5 of the inverter 16 becomes "L" at time t2.
” level to the “H° level, and at time t3 when the output D5 of this inverter 16 becomes higher than the circuit threshold of the inverter 21.24, the output D6. D
7 begins to change from the ``H'' level to the ``L'' level. As a result, the discharge MO5h run transistor Q28 turns off at the same time. At the next time [4], the output D2 of the inverter 15 changes from the ``L'' level to the At time t5 when the output D2 of the inverter 15 becomes higher than the circuit threshold of the inverters 17 and 20, the outputs D3 and D4 of these circuits change from the °H' level to "H# level".
It begins to change to L2 level. At this time, the MOS transistor Q19 of the inverter 20 receives the signal D2 from the inverter 20.
Since the output of the inverter 20 is delayed by 2°23, the output of the inverter 20 slowly falls to the aL level. Therefore, first, the charging MOS is
Transistor Q20 is turned on (time t5), and at the next time t7 (charging MO5) transistor Q2i is turned on. Therefore, the output signal Dout is “L” at time t5.
The current starts to rise slowly from the "H" level to the "H" level at time t8.The current between the times ts and tg when the output signal D out is inverted has a slope as shown in FIG. 10(b). According to this configuration, when the output signal D out is inverted, the charging MOS transistors Q20 and Q21 are sequentially turned on at predetermined time intervals, and the discharge is stopped. M.O.
Since the S transistors Q27 and Q028 are turned on sequentially at predetermined time intervals, sudden changes in the current for charging and discharging the load capacitance of the output section can be prevented, and the generation of self-noise that can cause circuit malfunctions can be prevented. can be suppressed. Therefore, the noise margin of the semiconductor integrated circuit device can be widened. Furthermore, since the charging MOS transistors Q20 and Q21 or the discharging MOS transistors Q27 and Q28 change from the on state to the off state at the same time,
The operation speed does not decrease significantly, and the charging MO
S transistor Q20°Q21 and 7tSMOS transistor Q27. Since Q28 is never turned on at the same time, no through current occurs. However, in order to prevent the above-mentioned through current, the inventors of the present application have developed a charging MO
8h run transistor, Q21 or discharge MO8+-
Ransistor Q27. Turning off Q28 rapidly
Charging MOS transistor Q20. Q21 or discharge M
OS transistor Q27. It was discovered that Q28 is a greater cause of self-noise than the noise generated when it is turned on. That is, the output signal D out is simply “Lo to 1H2
, or not only changes from 1H" to #L2,
There are cases where "L" data is output again from a state where "L" data was being output, or "H" data is output again from a state where "H" data was being output. When outputting "L" data again from the state where it was being output, the output changes to "L" due to the operation of the internal circuit.
After being temporarily charged in the "H" direction from the ° data, new correct "L" data may be returned. On the other hand, when outputting "H" data again from the state where "H" data was being output, the output is temporarily discharged from "H" data to "L" direction due to the operation of the internal circuit. Later, it may return to the new correct "H' data. Then, as mentioned above, the old data may be "Lo" and the new data may be "L".
In the case of ゛, it is charged in the ``H'' direction on the way, but it is not completely charged in the ``H'' direction.
It does not become H' and is discharged in the "L" direction from the middle. Similarly, 1, if the old data is "H" and the new data is 4H' as described above, it will be discharged in the aL1 direction on the way, but it will not completely reach 1L', and will be charged in the "H2 direction" on the way. In these two cases, we discovered that the most severe noise occurs when correct data is output from the intermediate level of "H" or "L". When incorporating the circuit into a system product, the power supply voltage V C and the ground potential VSS are each supplied from the power supply device to the output buffer circuit via wiring. Therefore, due to the inductance tV existing in the VCC wiring and the Vss wiring,
When a large current flows through these wirings, a large potential fluctuation occurs in the Vcc potential or the VSS potential. In other words, if we represent the inductance component existing in these wirings and the temporal change in the current flowing through the wiring as d i/d t, then as is well known, the wiring has the following equation: A potential change Δ■ occurs. Δv−L ・(d i/d t) −(1
) That is, the potential drop ΔV caused by this rapid change in current d i/d t becomes noise and becomes a cause of malfunction of the integrated circuit. Now, in the output buffer circuit shown in FIG. 8, consider a case where the output signal DOυt is temporarily charged in the "H" direction while changing from 1L degree to "L". When the signal D1 from the internal circuit is "H", the signals D6 and D7 are respectively "H", and the discharge MO5) transistors Q27 and Q
28 are respectively turned on. Also, the signals D3 and D4 become H2, respectively, and the MOS transistors Q20 and Q
21 are respectively turned off. Suppose now that the signal D1 becomes "Lo" temporarily. At this time, the signals D6 and D7 become "L", and the discharge MOS transistors Q27 and 0
28 are respectively turned off. The signal D3 becomes “H”,
The charging MOS transistor Q20 turns on and starts charging the output signal Dout in the "H" direction. A little later than this, the signal D4 becomes "L", and the charging MOS transistor Q21 turns on. In this way, since the charging MOS transistors Q20 and Q21 turn on with a time lag, the charging MOS transistor Q20, The change d i/d t in the current that charges the load capacitance of the output signal D out via Q21 is relaxed. However, when the signal D1 becomes 1H during this charging, the signals D3 and D4 almost simultaneously change to " becomes H'. At this time, charging MOS transistor Q20. Q21 turns off quickly, so until now the charging MOS transistor Q20. Q2] suddenly becomes zero, and its change d i /d t approaches infinity. As can be seen from the old formula (1), at this time ΔV is at its maximum and the power supply noise is at its worst. That is, in order to prevent through current, the output buffer transistor Q20. Q
21. Q27. Turning off Q28 quickly caused the most power supply noise. This will be explained in more detail below with reference to FIGS. 11(a) to 11(d). In the circuit of FIG. 8, when the signal D1 from the internal circuit is switched in a short period of time as shown in FIG. 11(a), during the period a in FIG. 11(a), the discharge MO8) transistor Q27. Q28 is on, charging MO
5) Transistor Q20. Q21 is off, but the 11th
As mentioned above, the period in FIG. Q28 are turned off at the same time, and the charging MOS transistors Q20Q21 on the selected side are turned on with a time difference. At this time, Fig. 11(b) and (C)
As shown in FIG. 2, a current flows from the VCC power supply to the output signal D out terminal at the same time as the potential of the output signal D out rises. During period C in FIG. 11(a), charging MOS transistor Q20°Q21 charges a large capacitor attached to the output signal D out terminal, and accordingly, a large current flows to V
Charge MOS transistor Q20 from CC power supply. It flows into the output signal Dout terminal via Q21. Then, as in period d in FIG. 11(a), when the signal D1 is switched while the output signal Dout is rising, the buffer transistors Q20, Q21. ,Q27
The selection and non-selection for Q28 are switched, and the 11th
During the period in FIG. 3(a), a situation opposite to that of 1 occurs, and the charging MOS transistor Q20. Q21 is turned off at the same time, and the selected side discharge MOS transistors Q27. Q28 turns on with a time difference. At this time, the charging MOS transistor Q20.021 receives the output signal Dou from the Vcc power supply.
Since the current that was flowing through the t end suddenly stops flowing, the current change d i / d t at the off time becomes close to infinity, as shown in Figure 11(d), and the maximum power supply noise occurs. It was the cause. Note that Fig. 12 Cl) to (d) show the operation when the signal D1 from the internal circuit in the circuit of Fig. 8 simply switches from "H' to "H'. Compared to the current change d i/d t , the current change d i/d t during off-time shown in FIG. 11(d) is significantly larger. (Problems to be Solved by the Invention) As described above, in conventional output buffer circuits, when the input signal changes in a short period of time, a sudden change in current occurs, especially when the output stage transistor turns off, and this causes voltage fluctuations. This has the disadvantage of causing malfunctions. The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to suppress potential fluctuations in the power supply voltage to a low level even if internal signals change in a short period of time. An object of the present invention is to provide an output buffer circuit that can prevent malfunctions. [Structure of the Invention] (Means for Solving the Problems) The output buffer circuit of the present invention includes a plurality of charging transistors connected in parallel and having a common connection point at one end connected to a first power supply, and other charging transistors. A plurality of discharge transistors are connected in parallel between the end side common connection point and a second power source, and a signal from an internal circuit is supplied to the gates of the plurality of charge transistors, and these charge transistors are connected at predetermined time intervals. a first delay means for sequentially setting the discharge transistors in a non-conducting state at a predetermined time interval, and supplying a signal from the internal circuit to the gates of the plurality of discharge transistors, and sequentially setting the discharge transistors in a non-conducting state at predetermined time intervals. and a second delay means. (Function) Multiple charging transistors will not turn off at the same time,
In addition, multiple discharge transistors are not turned off at the same time, but are turned off sequentially, so that the current change when the transistors are turned off d i
/ d t becomes smaller. (Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an output buffer circuit according to the present invention. That is, in the integrated circuit, the signal DS supplied from the internal circuit to the output buffer circuit is transmitted through the P-channel type MOS transistor TP2 and the N-channel type MOS transistor TP2.
) CMOS inverter A2 consisting of transistor TN2
supplied to The output D2 of the inverter A2 is supplied as one input of a two-man NAND gate 1 consisting of P-channel type MOS transistors TP3 and TP4 and N-channel type M, O5) transistors TN3 and TN4. MO8I-ransistor TP
9 and TPlo, and N-channel type MOS transistors TN9 and TNlo. The output control signal OUT is supplied as the other input of the two-person NAND gate 1, and the output control signal OUT is supplied as one input of the two-person NAND gate 2.
An inverted signal OUT of UT is supplied. The output D3 of the two-man power NAND gate 1 has one end connected to the power supply VCC.
It is supplied to the gate of a P-channel charging MOS+- transistor TP7 connected to the CMOS inverter A3. It is supplied via A4 to the gate of a P-channel charging MOS transistor TP8 whose end is connected to the power supply VCC. MOS) transistor TP7. The other end of TP8 is commonly connected. The CMOS inverter A3 includes a P-channel type MOS transistor TP5 and an N-channel type MOS transistor T.
The CMOS inverter A4 consists of a P-channel MOS transistor TP6 and an N-channel MOS transistor TP6.
S transistor TN6, and these CMOS inverters A3 . A4 is charging MOS transistor TP7
It operates as a delay circuit 3 that performs a delay operation to sequentially turn on or turn off TP8. The output D8 of the two-man gate 2 is connected to a MOS transistor TP7. N-channel discharge MOS transistor TN connected between the common connection point on the other end side of TP8 and the ground point VS2
CMOS inverter A5. A6, MOS transistor TP7. T
The signal is supplied to the gate of an N-channel discharge MOS transistor TN1B connected between the common connection point on the other end side of P8 and the ground point VS2. The CMOS inverter A5 includes a P-channel type MOS transistor TP11 and an N-channel type MOS transistor TN11, and the CMOS inverter A6 includes a P-channel type MO8! - transistor TP12 and N-channel type MOS) transistor TN12, and these CMOS inverters A5 . A6 operates as a delay circuit 4 that performs a delay operation to sequentially turn off or turn on the MOS transistors TN14 and TN13. In the above configuration, when the output control signal OUT and its inverted signal OUT are "L" or "H", the output D3 of the two-man power NAND gate 1 becomes "H5" and the charging MOS
The transistors TP7 and TP8 are turned off, and the output D8 of the two-person gate 2 becomes L", turning off the MOS transistors TN14 and TN13, so the output signal D out terminal becomes a high impedance state. On the other hand, when the output control signal OUT and its inverted signal OUT are H° and "L", the internal signal DS
is inverted by the CMOS inverter A2 and then inputted to the two-man NAND gate 1 and the two-man power gate 2, and the output D3 of the two-man power NAND gate 1 is supplied to the gate of the charging MOS transistor TP7, and passes through the delay circuit 3 to charge mMO5. ), and the output D8 of the double gate 2 is supplied to the gate of the discharge MOS transistor TN14, and is also supplied to the gate of the discharge MOS transistor TN13 via the delay circuit 4, so that the internal signal DS and In-phase output signal D
out is obtained. FIG. 2 shows waveforms at various nodes of the circuit shown in FIG. 1 during this operation. That is, when the output control signal OUT and its inverted signal OUT are "Hl" and "Lo", the transistor TN4
and TP9 are on, transistors TP4 and TNI
O is off, and at this time, the internal signal DS is “H”
to "L", the output D2 of inverter A2 becomes "L".
From l to 'H#. As a result, the output D3 of the two-person NAND gate 1 changes from "Hl" to "Lo," charging MO5)
The transistor TP7 turns on and starts charging the output signal D out terminal. At this time, during the delay time of the delay circuit 3, the charge @MO5) - the gate of the transistor TP8 is "L".
o is not transmitted and this transistor TP8 remains off, but the output D becomes "Lo" after the delay time of the delay circuit 3.
6 is transmitted to the gate of the XMOS transistor TP8, which turns on the transistor TP8. Furthermore, when the output of the inverter A2 goes from "L2" to "Hl", the output D8 of the two-man gate 2 goes from "Hl" to "L".
Then, the 4M0S transistor TN14 turns off and stops discharging from the output signal DouL terminal. At this time,
During the delay time of i1@circuit 4, L' is not transmitted to the gate of discharge MoS transistor TN13, and this transistor TN13 remains on. Therefore, at this time, V5sff is applied from the VccT4 source via the charging PViO5) transistor TP7 and the discharging MO3) transistor TN13.
A through current flows to the i source. This through current flows through the delay circuit 4
After the delay time, the output D10 becomes “Lo” and the discharge MO8I
- to the gate of transistor TN1.3 and continues until this transistor TN13 is turned off. When the output control signal OUT and its inverted signal OUT are "Hl2" L2, the internal signal DS is
goes from L'' to H'', the output D2 of the inputter A2
becomes “L2” from “Hl”. As a result, the output D8 of the two-person gate 2 changes from L'' to H2, and the discharge MOS transistor TN14 turns on to start discharging from the output signal Dout terminal.At this time, during the delay time of the delay circuit 4, 'H' is not transmitted to the gate of the discharge MOS transistor TN1B, and this transistor TN13 remains off, but the delay circuit 4
When the output DIO, which becomes °H" after a delay time of The output D3 changes from "Lo" to "Hl," and the charge MO8) transistor TP7 turns off to stop charging the output signal Dout terminal.At this time, during the delay time of the delay circuit 3, the charge MOS transistor TP7 turns off. "Hl" is not transmitted to the gate of TP8, and this transistor TP8 remains on. Therefore, at this time, charging 7115M0S transistor TP8 and discharging ~fOs
Vs from the V ccl'R source via transistor TN14
s7I! A shoot-through current flows to the source. This through current is caused by the charging M
O5) is transmitted to the gate of transistor TP8 and continues until this transistor TP8 is turned off. According to the output buffer circuit, the input signal is sequentially supplied to each gate of the plurality of charge MOS transistors to sequentially set the transistor to a conductive state, and the input signal is sequentially supplied to each gate of the plurality of discharge MOS transistors to sequentially set the transistor to a non-conductive state. Since it is set to a conductive state, a sudden increase in the VCC current does not occur when the output becomes "Hl", and a sudden decrease in the Vssri current does not occur when the discharge MOS transistor is turned off. Cuff No. 7 is sequentially supplied to each gate to sequentially set it to a conductive state, and an input signal is sequentially supplied to each gate of the plurality of charge MOS transistors to sequentially set it to a non-conductive state, so that the output becomes "Lo". There is no sudden increase in the Vss current when the transistor is turned off, and no sudden decrease in the Vccr current occurs when the transistor turns off. In addition, as described above, the effect of sequentially setting the plurality of discharge mMOS transistors to a non-conducting state is that the output signal D out changes in a short period of time while the output signal D out is being charged or discharged. For example, as shown in FIG. 11, the output signal D out
This appears when the voltage is temporarily charged in the "H" force direction while changing from "L" to "Lo". The charging current (Vcc current) and its temporal change d i /d t in this case are shown by dotted lines in FIGS. 3(a) and (b), and for comparison, the conventional output shown in FIG. The VCCt flow in the buffer circuit and its temporal change d i/d t are shown by solid lines. As can be seen from FIG. 3(b), according to this embodiment, the current change d i/d + when the output signal D out changes in a short period of time is drastically reduced compared to the conventional case. Note that in the conventional output buffer circuit, the output signal D
If the output signal Dout temporarily changes for a short period of time during charging and discharging of out, the circuit malfunctions due to power supply noise caused by the current change d i /d t when the charging or discharging MOS transistor is off. At this time, the output signal Do
υ1 is V ccy [! Since the potential is at an intermediate potential between the voltage level and the VSS potential, reverse data will be output again due to the influence of the power supply noise. Then, the MOS transistor that was turned on is turned off, and power supply noise is generated again. There is a mode in which the output buffer circuit oscillates due to self-noise due to repetition of such operations. However, according to the output buffer circuit of this embodiment, such an oscillation mode can also be avoided. Note that in the above embodiment, the charging MOS transistor TP7
and discharge MO9) A period in which a through current flows from the VCC power supply to the VSS power supply via the transistor TN1B, or
There is a period in which a through current flows through the charging MOS transistor TP8 and the discharging MOS transistor TN14 to the VCCCC power supply VSS power supply. However, in general,
Although through-current has long been considered a problem,
In the above embodiment, the through current temporarily eclipses the output signal D out for a short period of time during charging and discharging of the output signal D out,
It only occurs when the output is at an intermediate potential,
When the output signal D out changes from “Lo” to “H” or
Since almost no through current occurs when changing from "Lo" to "Lo," it does not pose a problem. This through current will be discussed below. An input section and an output section of another semiconductor integrated circuit are connected to the output section of the semiconductor integrated circuit on one wiring. For this reason,
There is a large parasitic capacitance in the output section of a semiconductor integrated circuit,
Even if the gate potential of the output buffer transistor changes,
The change in the drain potential is milder than the change in the gate potential. For example, in the circuit shown in Figure 1, the output (
Considering that No. J D out is charged from “Lo” to “H”, the charging 7ti MOS transistors TP7 and TP8
The gate potentials D3 and D6 of the charging MO3) become "L" one after another, and the transistors TP7 and TP8 turn on one after another.
The output signal Dout terminal is charged to H", but the output signal D
Since out charges the parasitic capacitance of the output section, the discharge MO
The rise in the drain potential of the S transistor TN13 is slow;
In other words, since this drain potential is low, at this time, the discharge M
O3) The gate potential D 1.0 of transistor TNi3 is “
Even if the discharge to Lo is slow, the current flowing through this discharge MOS transistor TN13 is small. Therefore, charging bi
Vss? from the VCC power supply via the os transistor TP7 and the discharge 1v10S transistor TN13. The through current flowing to the M source can be kept small. As shown in Fig. 11, such a through current can charge and discharge a large parasitic capacitance in the output section even if the output signal D out changes temporarily for a short period of time during charging and discharging of the output signal D out. Even if there is a through current as described above, this through current will not cause a large change in the output current change di/dt; rather, the current change d i / dt will be As in the above embodiment, the effect of delaying the turn-off of the transistor is much greater. As can be seen from the old equation (1), the potential variation ΔV is determined by the current variation d i /d t. In other words, even if a large current flows steadily, if there is no temporal change in the current, d i/d t is zero, the above-mentioned ΔV is also zero, and no power fluctuation occurs. No matter how small the current, if the rate of change in the current is large, d i /
dt becomes large, and the above-mentioned ΔV also becomes large. That is, as in the above embodiment, the current change d i /d
Reducing t leads to smaller power supply fluctuations, and rather, it is better to let the through current flow to a certain extent to reduce d.
This makes it possible to reduce i/dt. In the above embodiment, the case where there are two charging MO3 transistors and two discharging MOS transistors has been described, but it goes without saying that there may be more than two transistors. Further, although the delay circuit 3 and the delay circuit 4 each consist of a two-stage CMOS inverter in the above embodiment, it goes without saying that they may have other configurations. Furthermore, the charging MOS transistor T
Gate potential D3 of P7 and charging MOS transistor T
The speed at which the gate potential D6 of P8 changes from 1L" to "H" is slowed down, and the speed at which the gate potential D8 of discharge MO3) transistor TN14 and the gate potential DIO of discharge MOS transistor TN13 change from "Ho" to "L" is slowed down. Then, it becomes possible to further suppress the change in VSS current d i/d t when the discharge MO8) transistor turns off. Similarly, the radiation TjX1MOS transistor T
The speed at which the gate potential D8 of N14 and the gate potential DIO of the discharge MO8h run transistor 3 change from 'La to Ho is slowed down, and the gate potential D3 of the charge MO3) transistor TP7 and the gate potential D6 of the charge MOS transistor TP8 are set to H' By slowing down the speed at which the charge MOS transistor changes from to "L", it becomes possible to further suppress the change in V ce lightning current d i/d t when the charging MOS transistor is turned off. The output buffer circuit of the integrated circuit according to the example is shown. That is, the signal DS supplied from the internal circuit to the output buffer circuit is a P-channel type MO
S transistors TP3 and TP4 and N-channel type M
OS) is supplied as one input of a two-man NAND gate 1 consisting of transistors TN3 and TN4, and
P-channel type MOS transistors TP9 and TP]
0 and N channel type MOS transistors TN9 and T
It is supplied as one input of a two-person gate 2 consisting of NIO and NIO. The output control signal OUT is supplied as the other input of the two-man NAND gate 1, and the inverted signal OUT of the output control signal OUT is supplied as the other input of the two-man power gate 2. The output D3 of the two-person gate 2 is supplied via a CMOS inverter A7 to the gate of a P-channel MOS transistor TP7, one end of which is connected to the power supply VCC. In addition, the output D3 of the two-man gate 2 is connected to the gate of an N-channel type MOS transistor TN15 whose one end is connected to the ground point Vss, and to the gate of a P-channel type MOS transistor TN15 whose one end is connected to the other end of this MO3I-transistor TN15. It is supplied to the gate of the MOS transistor TP13, and the CMOS inverter A8. A9 is supplied to the gate of a P-channel MOS transistor TP14 connected between the other end of the MOS transistor TP13 and the power supply Vce, and one end of the connection point between the MOS transistor TN15 and the MOS transistor TP13 is connected to the power supply VCC. P-channel type charging MO8) transistor TP8
is supplied to the gate. MOS transistor TP7. T
The other end of P8 is commonly connected. CMOS inverter A, 8. A9 is a charging MOS transistor TP7゜TP
a to turn off 8 sequentially! It operates as a delay circuit that performs a delay operation. The output D13 of the two-man NAND gate 1 is connected to the MOS transistors TP7. through the CMOS inverter AIO. T.P.
N connected between the common connection point on the other end of 8 and the grounding point VS2
It is supplied to the gate of a channel type discharge MOS transistor TN14. In addition, the output D1 of the two-person NAND gate 1
3 is a P-channel type M whose one end is connected to the power supply VCC.
O5I - the gate of transistor TP15 and this MO
It is supplied to the gate of an N-channel type MOS transistor TN17 whose one end is connected to the other end of the S transistor TP15, and is also supplied to the gate of the CMOS inverter A1.1. A12
is supplied to the gate of an N-channel MOS transistor TN18 connected between the other end of the MOS transistor TN17 and the ground point VS2.
The connection point of P15 and MO9h transistor TN17 is
MOS transistor TP7. N-channel discharge MO connected between the common connection point on the other end side of TP8 and the ground point VS2
5) Supplied to the gate of transistor TN1.3. CM
The OS inverters All and A12 operate as a delay circuit that performs a delay operation to sequentially turn off the discharge MOS transistors TN14 and TM01. In the above output buffer circuit, unlike the output buffer circuit of the above embodiment, the plurality of charge MOS transistors are set to conductive state almost simultaneously, and the plurality of discharge MO5h
The transistor is sequentially set to a non-conducting state by sequentially supplying an input signal to each gate. Therefore, a sudden decrease in the VSS current does not occur when the discharge MOS transistor is turned off. Furthermore, the plurality of discharge MoS transistors are set to a conductive state almost simultaneously, and the plurality of charge MOS transistors are sequentially set to a non-conductive state by sequentially supplying an input signal to each gate. Therefore, a sudden decrease in Vcc current does not occur when the charging MOS transistor is turned off. FIG. 5 shows waveforms at various nodes of the circuit shown in FIG. 4 during operation of this output buffer circuit. As mentioned above, the noise when the output buffer transistor is turned off is rather larger than when it is turned on. Therefore, even if multiple charging transistors in the output buffer circuit are turned on at the same time and multiple discharge transistors are turned on at the same time, if they are turned off in sequence when they are turned off, the noise will be smaller than before, and the parasitic capacitance that exists in the output will be reduced. Can be charged and discharged quickly. Although the present invention has been described using the 0M05 circuit, it is generally applicable to any type of output buffer circuit of a semiconductor integrated circuit. [Effects of the Invention] As described above, according to the output buffer circuit of the present invention, a plurality of charging transistors are sequentially set to a non-conducting state at a predetermined time interval, and a plurality of discharging transistors are sequentially set to a non-conducting state at a predetermined time interval. By setting this state, potential fluctuations in the power supply voltage can be suppressed to a low level even if the internal signal changes in a short period of time. Furthermore, by sequentially setting the plurality of charging transistors to a conductive state at predetermined time intervals and sequentially setting the plurality of discharging transistors to a conductive state at predetermined time intervals, sudden changes in current when the output changes can be prevented. Since this does not occur, potential fluctuations in the power supply voltage can be suppressed to a low level. Further, by allowing a certain amount of through current to flow when the output changes, sudden changes in current are prevented, so potential fluctuations in the power supply voltage can be suppressed to a low level. Therefore, according to the present invention, it is possible to obtain an output buffer circuit that can prevent malfunctions of other circuits.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an output buffer circuit according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the circuit in FIG. 1, and FIG. 4 is a diagram showing an output buffer circuit according to an embodiment of the present invention. 5 is a diagram for explaining the operation of the circuit in FIG. 4, FIG. 6 is a diagram showing a conventional output buffer circuit, and FIG. 7(a) and (b) is a diagram for explaining the operation of the circuit in FIG. 6, FIG. 8 is a diagram showing a conventional improved output buffer circuit, and FIGS. 9(a) and (
b) and FIGS. 10(a) and (b) are diagrams for explaining the operation of the circuit in FIG. 8, and FIGS. 11 and 12 are diagrams for explaining the operation of the circuit in FIG. 8, respectively. FIG. 7 is a diagram for explaining operations when switching occurs and when not switching. TP7. TP8・・・・・・MMO5h transistor,
TP 13. TP 14...---Release 1riMOS transistor, DS... Signal from internal circuit, D
out...Output signal, 3.4, 41.42.
...Delay circuit, A2-A12...Inverter. Applicant's agent Patent attorney Takehiko Suzue Time - DS Figure (a) Figure (b) Figure 4 t+ 42 j3t4t5t6t7t8 hours. Diagram (a) ■ T (J Kō (a) Time → Time → Figure 11

Claims (3)

[Claims] (1) A plurality of charging transistors that are connected in parallel and whose common connection point on one end side is connected to a first power source, and a plurality of charging transistors that are connected in parallel between a common connection point on the other end side of these charging transistors and a second power source. a first delay means for supplying a signal from the internal circuit to the gates of the plurality of charging transistors and sequentially setting the charging transistors to a non-conducting state at predetermined time intervals; and second delay means for supplying the signal to the gates of the plurality of discharge transistors and sequentially setting these discharge transistors to a non-conductive state at predetermined time intervals. (2) The first delay means sequentially turns on the plurality of charging transistors at predetermined time intervals, and the second delay means sequentially turns on the plurality of discharge transistors at predetermined time intervals. 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is set to the state. (3) The first delay means and the second delay means are arranged such that at least one transistor among the plurality of charging transistors and at least one transistor among the plurality of discharging transistors are connected to each other when output data changes. 3. The output buffer circuit according to claim 1, wherein the output buffer circuit is controlled to be turned on at the same time.